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BUSSES, MODULES and NETS

lostwithouthope

Hi everone,

 

maybe someone can help me. I'm pretty familiar with but it seems like I cant solve the following problem: (I'm working with EAGLE 7.7)

 

I've created a MODULE named DAC_CHANNEL and added a "bus" PORT called DB[0..13] to it.

I've added 16 DAC_CHANNEL MODULES to my schematic, created 4 BUSSES (DAC_DATA0:DB[0..13]; DAC_DATA1:DB[0..13]; DAC_DATA2:DB[0..13]; DAC_DATA3:DB[0..13]) and connected 4 MODULES to each BUS.

THIS works perfectly, now the PROBLEM:

I need to connect the BUSSES to the PINS of a FPGA. So I use NET to connect PINS to a BUS and get a list with the members of the BUS (DB0 to DB13) but selecting one of them will name the NET only DB0 but the correct name would for instance DAC_DATA0:DB0.

So cannot connect anything to this BUSSES except the MODULES, even manually naming a net DAC_DATA0:DB0 doesn't work as I'm not allowed to use ':' in names but when I look up the name of the net between the modules in the PCB editor it is named DAC_DATA0:DB0.

 

Attached you find a picture of my problem

 

I would be gratefull for any hints.

Cheers Reinhard

 

Nachricht geändert durch Reinhard Klambauer

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  • 0

    Hi Reinhard,

     

    I just tested this out on one of my boards and it seems to be ok. What you need to do is use a generic bus name within the module and then at the top level where you connect the modules to the FPGA then manually name the busses such that they get the correct individual names e.g. DAC_DATA0:DAC_DATA0_DB[0..13], DAC_DATA1:DAC_DATA1_DB[0..13] etc.

     

    I know it's a pain having to do that, I think there should be an option to enable to bus name to prefix the signal name but currently this doesn't happen. If you do what I have suggested above then you should have correctly unique signals for each of your DAC's to your FPGA.

     

    Best regards,

     

    Rachael

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  • 0

    Hi Reinhard,

     

    I just tested this out on one of my boards and it seems to be ok. What you need to do is use a generic bus name within the module and then at the top level where you connect the modules to the FPGA then manually name the busses such that they get the correct individual names e.g. DAC_DATA0:DAC_DATA0_DB[0..13], DAC_DATA1:DAC_DATA1_DB[0..13] etc.

     

    I know it's a pain having to do that, I think there should be an option to enable to bus name to prefix the signal name but currently this doesn't happen. If you do what I have suggested above then you should have correctly unique signals for each of your DAC's to your FPGA.

     

    Best regards,

     

    Rachael

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