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Amega328p-au shorted pins ?

n2nxz

Finally motivated myself into trying Eagle files only to see my original instincts told me NOT to bother.

The last thing I expected was not finding common components in the library.My first mistake to assume that an Atmega328p-au would be one of the easiest to find.Not so and had to search the ends of the earth to find it and manually place it into the LIBR directory.After a 4 hour search and finally having this IC in my schematic layout I now see"shorts on several pins of this chip in the BRD window.The worse possible places no less on 3.3v and ground

I can probably modify this file but now getting far deeper into a simple project I thought would be straight forward.

Is it a software glitch causing this or a bad library file ?

Anyone know where to find a working Atmega328p-au footprint

See attached screen shot of the issue.

image

  • 0 in reply to rachaelp

    Just sharing to the group for the records on this topic.

    No hurry for me and do not expect anyone to solve my issues.I needed to walk away from it awhile and clear my head.

    Still waiting for the final components to arrive anyhow so will be some time before planning a build.

    I am sure someone with experience in Eagle will know what I am doing wrong...most likely the fact I need to just keep working on it and learn more.

    Jim

  • 0 in reply to n2nxz

    Decided to try one more time tonight.

    This time I used the full size board work area without trying to squeeze everything in for a quick run.

    Also read this issue related - http://www.bot-thoughts.com/2013/09/eagle-sudden-clearance-errors-isolation.html

    Tried the solution in the post and also ran through my entire design rules settings.

    Whatever it was I get NO DRC errors now.

    Since I changed 3 major settings,not sure which it was causing my headaches.

    Tomorrow going to try rewriting the schematic the way I originally planned and shrink it down to a reasonable size.

    See what happens.

    Jim

  • 0 in reply to n2nxz

    With the schematic re-drawn like I want,went ahead and tried to make another board.

    Autorouting shows some connections bad.A run of the DRC once again shows the same issue regarding clearance on the Si5153a IC.

    I am am bit confused about auto routing since there are few options.This time,I set it up with EFFORT set to high rather than default.

    I still have a vague knowledge in where this should be anyhow.Still searching out more info.

    image

  • 0 in reply to n2nxz

    Hi James,

     

    I've just had a quick look at your latest schematic and made a quick board with it.

     

    The first thing to note is that your silk screen elements in the board your a mixture of vector (correct) and proportional (incorrect) and this will lead to your silk screen on your PCB not looking like you expect when you get your boards back. To have clear and consistent silk screen legends which match the board you must you vector for all your parts. Now, this isn't your fault exactly, its down to relying on poor quality parts sourced from either the bundled "free" libraries or from the internet.

     

    Now, onto your DRC problem. When I ran your schematic through to a board and ran DRC, if I don't load a .dru file from the board manufacturer and rely on the defaults, then I get a bunch of clearance errors. I then went and loaded the basic 2-layer .dru file from Eurocircuits and ran DRC and it passed without error. What fab house are you using for your boards? Do they provide an EAGLE .dru file (or files) for their capabilities? If so then load this and run DRC. Then if there are still any errors, examine them on a case by case basis to determine if you really need to worry.

     

    With regards the auto router, well you can use it if you must but you wont get the best result. I think it's best used as a tool to help manual routing. Manual is the way to go really and then you can use the auto-router selectively to help you route simple but very repetitive groups of traces. First thing to do though it to get the placement right as that is 90% of the battle. Move things around, rotate etc, even update the schematic if needed to get the air wires to run a cleanly as possible. Remember to run ratsnest regularly so you can see how things are improving. Once you are happy with placement you can then start to route things in. I get critical nets like clocks routed in first, then work your way through the rest, leaving the least critical to last. Make sure your power and grounds are done well and do make sure you have adequate decoupling caps. I don't see any bulk or bypass caps in your design. I know you are trying to save weight but you might need a few. internal power/ground planed in the board will help there too, although again they will add a little weight.

     

    Best Regards,


    Rachael

  • 0 in reply to rachaelp

    I will start by finding the EAGLE .dru files which I need to check with Oshpark or whoever has the best help in this project.

    Going to look all this over thoroughly and see about making up new footprints as well.

    Seems too bad that the footprints I have in my library do not work properly.

    Most likely some challenges ahead until I learn this stuff.

    I appreciate you looking this over and for your time.Hopefully this post will help others not to mention a great reference point for myself during this task.

    Jim

  • 0 in reply to n2nxz

    Guessing I need this 2 layer .dru file if I am using Oshpark for my PCB`s ?

    OSH Park Docs ~ Eagle Design Rules files.

  • 0 in reply to n2nxz

    Just to update my progress,I have seemed to be learning a bit and progressing with this project.

    The DRU files from Ohpark loaded seemed to help greatly.

    Also zeroed the NET CLASSES using default.Eventually they are set to 5mil.

    So the above issue from that link was great help as well.

    After some minor issues was able to produce a BRD file to upload to Ohpark.I get ZERO DRC errors now and the Si5351a chip (U1) finds traces like it should.

    Now to look over and double check everything and build a bread board design for programming and testing.If all goes well,will order a few PCB`s and try my hand with SMD.

    Board - https://644db4de3505c40a0444-327723bce298e3ff5813fb42baeefbaa.ssl.cf1.rackcdn.com/09256ea28b82b0e705c19685ab301150.png

    Bottom - https://644db4de3505c40a0444-327723bce298e3ff5813fb42baeefbaa.ssl.cf1.rackcdn.com/2c687c3b7069769618305c3053786940.png

    Thank you here for all the help and patience.

    Jim

  • 0 in reply to n2nxz

    Hi James,

     

    I'm glad you are learning and making progress image Hopefully you are finding it more rewarding now you are starting to see some results. I just had a quick peek at the two images you posted up. I have a couple of comments.

     

    Firstly, your power net is routed around the board with a really skinny trace. I wouldn't recommend this, especially as you don't appear to have any decoupling caps at the IC pins. I think this is likely to end up being problematic. If it were my board I would try and use polygon fills top and bottom to get your Vcc and GND connected around the board as much as possible. Obviously with a 2 layer board you're going to end up cutting up any polygon fills with all the other traces running around but I would give this a try to see how it works.

     

    Secondly, it's obviously auto routed and there are several places where the nets just go really close to things when there is bags of room for them to have a little more clearance. Examples would be the traces running very close to X2 and the ones around J1 but there are plenty of examples all over the board. I'd recommend you have a go at manual routing on the board, you'll pretty much always get a much nicer result.

     

    Best Regards,


    Rachael

  • 0 in reply to rachaelp

    I moved to my programming issues for the time and was worried because after all...if I can not program the 328 it is useless.

    But yes on your comments in regards to the traces running long.I was just happy to get a BRD file and test it out image

    I can now move stuff around and tighten everything up and add or remove other components.

    The schematic is designed around an existing circuit and using identical components.I do see room for decoupling caps to the 328 IC.

    I have not used them in previous build except for the GPS and Si5351 for the obvious reason the y produce RF.I had issues in this regard and is why they were added and the circuit runs well as it is.But to be safe,maybe I will add them to the 328 too.

    I was not too worried about the power traces being so small since the input voltage will be merely a 3.7 lipo @ 100mah then into the 3 voltage regs for an output of 3.3v.I used 3 regs for each module,328/gps and si5351 as to not stress one for everything.My previous build was using 5v directly from 5v boost module from a lipo 3.7v/100mah battery.No voltage regulators except the onboard regs of the 5351 and GPS.The 328 IC was ok since it runs 5v max anyhow.This board was to emulate the identical circuit only eliminating the 5v boost module to reduce weight and components needed.

    My GPS modules arrived and weigh only .9 grams where the prebuilt GPS is like 7 grams.The Si5351 prebuilt for 5v weighs about the same and that has be drastically reduced as well.So big time gains regarding weight loss on this.

    I should mention it also will have solar cells attached.The battery and solar input have 3 connections one for batt and the other for solar cells.

    Added a blocking diode between batt/soalr to prevent voltage from absorbing into the cells.It seems to work great that way.

    The cool part is the batteries I buy are tiny and have a built in over charge circuit...ready to use.

    Thanks again for you assistance and comments.VERY helpful and will come back to post my revised board and maybe a working board !!