Description of errors in ERC / DRC

Hi Alex,

There is a description of the DRC error messages in the manual chapter 6.4:

Angle:

Tracks are not laid in an angle of 0, 45, 90 or 135°. This check can be switched on or off in the Design Rules (Misc tab). Default: off.

Blind Via Ratio:

The limit of the ratio of via length (depth) to drill diameter is exceeded. In this case you have to adjust the via's drill diameter (Design Rules, Sizes tab) or the layer thickness of your board (Design Rules, Layers tab).

Clearance:

Clearance violation between copper objects. The settings of the Design Rules' Clearance tab and the value for Clearance of a given net class are taken into consideration. Of these two values the higher one is taken for

checking. In addition the Isolate value will be taken into consideration for polygons with the same rank and polygons which are defined as a part of a Package. To deactivate the clearance check between objects that belong to the same signal, use the value 0 for Same signals in the Clearance tab. Micro Vias are treated like wires. The clearance value for wire to wire applies in this case.

Dimension:

Distance violation between SMDs, pads, and connected copper objects and a dimension line (drawn in Layer 20, Dimension), like the board's outlines. Defined through the value for Copper/Dimension in the Design Rules'

Distance tab.Setting the value Copper/Dimension to 0 deactivates this check. In this case polygons do not keep a minimum distance to objects in layer 20, Dimension, and holes! The DRC will not check if holes are placed on tracks then!

Drill Distance:

Distance violation between holes. Defined by the value Drill/Hole in the Design Rules (Distance tab).

Drill Size:

Drill diameter violation in pads, vias, and holes. This value is defined in the Design Rules' Sizes tab, Minimum Drill. It is also possible to define a special drill diameter for vias in a given net class (CLASS command, Drills). In this case the higher one is used for the check.

Invalid Polygon:

Reason is a not properly drawn polygon contour. As soon as the contour lines are overlapping or even crossing, the polygon can't be calculated correctly. Change the polygon's contour in the Layout Editor or in the Library, if it is part of a Package. The RATSNEST command shows this error message, as well.

Keepout:

Restricted areas for components drawn in layer 39, tKeepout, or 40, bKeepout, lie one upon another. This check is executed only if layers 39 and 40 are displayed and if the keepout areas are already defined in the Package Editor of the library.

Layer Abuse:

Layer 17, Pads, or 18, Vias, contain objects which are not automatically generated by EAGLE. Probably you drew something manually in these layers, although they are reserved for pads and vias. Better move such objects into another layer.

Layer Setup:

This error is shown if an object in a layer is found that is not defined by the Layer setup. The same for vias that do not follow the settings of the Layer setup, for example, if a via has an illegal length (Blind/Buried vias).

Micro Via Size:

The drill diameter of the micro via is smaller than the value given for Min. Micro Via in the Sizes tab.

No Vector Font:

The font check (Design Rules, Misc tab) recognizes text in a signal layer which is not written in EAGLE's internal vector font. If you want to generate manufacturing data with the help of the CAM Processor the texts, at least in the signal layers, ought to be written in vector font. This is the only font the CAM Processor can work with.  Otherwise the board will not look the same as it is shown. Change the font with the help of the command CHANGE FONT or use the option Always vector font in the Layout Editor's Options/User Interface menu: If activated, the Layout Editor shows all texts in vector font. This is the way the manufactured board will look like.

Activating the sub-option Persistent in this drawing saves the setting in the drawing file. If you send the layout file, for example, to the board house you can be sure that the vector font will be displayed also at his system.

No real vector font:

The font check (Design Rules, Misc tab) recognizes text in a signal layer which is not written in EAGLE's internal vector font although it is displayed as vector font in the Layout Editor window. This situation arises if the

option Always vector font in the menu Options/User Interface is active. See error message No vector font for further details.

Off Grid:

The object does not fit onto the currently chosen grid. This check can be switched on or off in the Design Rules' Misc tab. The default setting is off, because as soon as trough-hole and surface-mount parts are used together it's not easily possible to find a reasonable common grid. The check is set off by default.

Overlap:

DRC reports this error as soon as two copper elements with different signals touch each other.

Restrict:

A wire drawn in layer 1, Top, or 16, Bottom, or a via lies in a restricted area which is defined in layer 41 or 42, t/bRestrict. If restricted areas and copper objects are defined in a common Package, the DRC does not check them!

Stop Mask:

If there are silkscreen objects drawn in layers 21, 25, 27 for components on the Top layer, and 22, 26, and 28 for components on the Bottom layer overlapping the area of a solder stop symbol generated in layer 29 and 30,

the DRC reports a Stopmask error. You have to display the corresponding layers to activate this check! Please keep in mind that this check always takes the vector font as basis for the calculation of the required space. This is the font type the CAM Processor uses for manufacturing data generation.

Width:

Minimum width violation of a copper object. Defined by Minimum Width in the Design Rules (Sizes tab) or, if defined, by the track parameter Width of a referring net class. The higher one of the given values will be taken for this check. Also the line width of vector font texts in signal layers will be checked.

Wire Style:

The DRC treats a line (wire) whose Style is LongDash, ShortDash or DashDot in the same way as a continuous line. If a wire drawn with one of these styles is laid as a signal, the DRC reports a Wire Style error.

Concerning ERC there is no description of the messages.ERC checks logical things in the schematic. The messaged are about connections, supply pins and so on. There is no rule what you have to do with a certain message. Simply read it and decide whether this is okay or not.

The same with DRC: It can happen that you say: This is done by intention. If this is the case, approve the message and that's it.

Regards,

Richard