1. When polygon is created in eagle6.4.0 lite and 6.2.0 lite, it calculates correctly. Any layer. Any polygone wires.
2. When the same polygon is renamed into a some wire name from schematic, it does not calculate anymore at all. Any layer. Any polygone wires.
3. There is some 12mils limitation somewhere in the programe regarding width of polygone wires that cold not be found… Any layer.
What to do about that?
1. There is no pad/smd/via inside the polygon contour that has the same name as the polygon and therefore it should be filled. The polygon should connect to the same name line which connects to the same name connector pin. I do not even see ratsnest towards the polygons and that I can not understand... It behaves like polygones are not as lines. But I can highlight them usig show command. Where else can I do?
A give you a picture of the situation. A hilighted bits are hilited from schematic, therefore connection is there. But no ratsnest is visible among polygons. Yellow line does not connect center polygons, nor are conected outer ones which all bear different names and are highlitable from schematic.
Blue polygon is the one I added later as an additional test, that was trigger to post this situation, which differs from description from docs.
2. Regarding thickness of the polygone lines. For now and until now I do not recognize any parameter, that the thickness of the polygone lines is checked against, in the DRC (default) error or settings in Design Rules or in the net classes. I can only change the thickness of the polygone line itself so that DRC (default) error checker does not find such fault. I can probably override this, but this is not the issue, as it does not even calculate the polygones, at any thickness of the polygone lines, and I do not know what to blame...
