So, here I want to know "how to route or fanout the ball grid array of spartan 7 FPGA (XC7S100FGGA676 ) which has 676 pins?". Can anyone help me out?
Actually, I am using Autodesk Eagle version 9.1.0.

Question

So, here I want to know "how to route or fanout the ball grid array of spartan 7 FPGA (XC7S100FGGA676 ) which has 676 pins?". Can anyone help me out? Actually, I am using Autodesk Eagle version 9.1.0. 
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rachaelp · Answer

How many layers is your board? How much of the IO is used vs unused? What are any signal integrity requirements which will drive numbers of GND layers? First things first... Do NOT under any circumstances be tempted to try using the BGA autorouter as it's utterly garbage... I tried it and it was awful. I write a blog post on it here: https://www.element14.com/community/community/eagle/blog/2017/08/29/eagle-v8-taming-the-bga-router In that linked blog I do show you some basic manual breakout techniques which give an idea of how to start thinking about getting many traces out in minimal layers. Anyway. I've routed out a pretty busy one of these for a Kintex 7 in a 900 ball package. It was a 8-layer board initially with exclusively through vias, no blind or microvias, so the cost wasn't high. So there are a few things to do which make life easier and then things which you do before everything else. The following lists these things out. 1) Get your BGA footprint right. The IPC generator in EAGLE/Fusion does fine, but go manually add solder paste/mask layer data as it relies on the built in generation which is useless for a BGA. 2) Always use rounded pads on your components, including passives. This helps solderability and has the added bonus of allowing small passives to fit between the vias underneath the BGA. 3) Confirm amount of decoupling you need. The Xilinx FPGA's actually have some decoupling embedded within the device itself so less is needed on the board which makes life easier. (e.g. https://www.xilinx.com/support/documentation/user_guides/ug483_7Series_PCB.pdf or https://www.xilinx.com/support/documentation/user_guides/ug583-ultrascale-pcb-design.pdf ) 4) Set your PCB grid to half the pitch of the BGA so I think these are 1mm parts off the top of my head so set your grid to 0.5mm. 5) Set up the via size and default trace width. I used a 10mil drill and 18mil diameter which gives a 4mil annular ring. and a 6mil trace width for the breakout. The PCB house were happy with these sized vias limited to just the BGA breakout area. 6) Use the fanout tool to breakout all the pins. Then curse as it's not grid aware and puts them all slightly off grid. Use the MOVE command with groups of left half, right half, upper half, lower half to shift them back onto the grid properly. Note, if you have a lot of unconnected IO pins and you want to provision for them to be connected in later you can ensure you have a breakout for them by putting a short wire on each unused pin in the schematic then the fanout tool will add a breakout for them. 7) Add the GND fills on the layer(s) chosen. If you also have one or two contiguous power layers add these too at this point as it'll clean up visibility. 8) Place your big bulk decoupling caps top side around the outside, place the small bypass caps underneath. You'll see now why I said use rounded pads as this actually gives just about enough clearance to squeeze in between the vias which makes life much easier. Plonk them down between PWR/GND vias and connect them straight in. 9) Route your clocks out. 10) Route any diff pairs out. 11 ) Route any other critical nets out. 12) Route the rest out. Below is an image showing the top layer, breakout, and bottom layer decoupling on one of my boards for the 900 ball variant. If you have any more specific questions let me know. The MOVE command line for getting the vias back on grid can be fiddly if you aren't used to using it so let me know if you get stuck with that. Best Regards, Rachael

jc2048 · Answer

This might help you get started, if you haven't read it already https://www.xilinx.com/support/documentation/user_guides/ug1099-bga-device-design-rules.pdf

wolfgangfriedrich · Answer

Here is another good document to read:

https://www.latticesemi.com/view_document?document_id=671

It is a 1mm ball pitch and not all signals are used (although 2 sides look pretty busy), so you might get away with 8 to 10 layers either with blind and burried vias or very fine pitch trace and clearance (3mil/3mil or maybe 4/4). If you have a lot of special signals (DDR memory bus, differential pairs) the layer count can go up quickly as you might need more GND planes.

Good luck.

Jan Cumps · Answer

rachaelp , didn't you use to do this as your job? Both Eagle PCB design and FPGA fanning-out?

So, here I want to know "how to route or fanout the ball grid array of spartan 7 fpga (XC7S100FGGA676) which has 676 pins?". Can anyone help me out?

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