I am trying to cramp as much design I can in a small PCB to reduce costs.
I have properly made each design with no DRC errors,
and then used the panelized.ulp procedure to made the designs adequate for panelizing.
I got a huge amount of width errors, whatever the option I take.
I have properly made each design with no DRC errors,
and then used the panelized.ulp procedure to made the designs adequate for panelizing.
But when I import several on them in my new board design,
I got a huge amount of width errors, whatever the option I take.
Can you help ?
Thanks
