Hello.
I make multilayer PCB with blind and buried vias. I have a problem with rule verification.
The rules was made for each layers separately . That way is convenient for my design.
for example 0.1mm:
There are blind via (TOP- Signal layer 1) and buried via (Signal layer 1- Signal layer 6 ). Both of vias are on the Signal layer 1 with distance 0.06mm.
1 Checking design rules does not give any errors though the gap is only 0.06mm on Signal layer 1.
2 If I use a general rule for all leyers I will get the correct сlearance constraint error.
Why the rule does not work in the first case? Could you help me with rules for separate layers.
