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Design Rule Verification

dmitriy2020 over 4 years ago

Hello.

I make multilayer PCB with blind and buried vias. I have a problem with rule verification.

The rules was made for each layers separately . That way is convenient for my design.

for example 0.1mm:

There are blind via (TOP- Signal layer 1) and buried via (Signal layer 1- Signal layer 6 ). Both of vias are on the Signal layer 1 with distance 0.06mm.

1 Checking design rules does not give any errors though the gap is only 0.06mm on Signal layer 1.

2 If I use a general rule for all leyers I will get the correct сlearance constraint error.

Why the rule does not work in the first case? Could you help me with rules for separate layers.

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voltsandjolts over 4 years ago in reply to dmitriy2020 +1

I think there might be a bug. To me, it looks like if you have a clearance rule specifying layer (e.g. Top Layer - ALL) then: Track to track is checked OK Track to via is checked OK Via to Via is NOT checked…

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voltsandjolts over 4 years ago

You can add net classes to get different clearances as required.
You can use the net class directive on the schematic or, if you need lots of those, it's easier to use net blankets:
https://www.eevblog.com/forum/circuit-studio/net-blankets-for-circuitstudio/
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dmitriy2020 over 4 years ago in reply to voltsandjolts

There is online DRC. I tried several variants :
still not getting any error
Please check CsPcbDoc :

Attachments:
new_pcb_test.zip
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voltsandjolts over 4 years ago in reply to dmitriy2020

I think there might be a bug.
To me, it looks like if you have a clearance rule specifying layer (e.g. Top Layer - ALL) then:
Track to track is checked OK
Track to via is checked OK
Via to Via is NOT checked

Edit:
Ah, its not a bug, it needs another rule.
Vias (and TH-pads) are "Multi-Layer" objects so a rule like [Top Layer - ALL] does not apply to them. They are not on the "Top Layer" ... not intuitive logic I would say, but thats the way it is.

Create an additional rule for via/pad clearance to other vias/pads.
(Enter -1 for Minimum Clearance then enter clearance values)
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dmitriy2020 over 4 years ago in reply to voltsandjolts

It is worth noting Your rule is not for signal layer 1. No doubt, general rules are work well.

I think the bug appears for blind and buried vias on selected layers only. The rule is not checked between rings of vias .
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voltsandjolts over 4 years ago in reply to dmitriy2020

Correct, the above rule and clearance apply to all layers.
So, you would need to use worst case clearance value for all layers.
I can't see a way to to specify via-to-via clearance differently for each layer.
Please post here if you find a way.

Are you saying the rule I posted above is not applied to blind and buried vias?
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voltsandjolts over 4 years ago in reply to dmitriy2020

Correct, the above rule and clearance apply to all layers.
So, you would need to use worst case clearance value for all layers.
I can't see a way to to specify via-to-via clearance differently for each layer.
Please post here if you find a way.

Are you saying the rule I posted above is not applied to blind and buried vias?
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dmitriy2020 over 4 years ago in reply to voltsandjolts

Thanks for the help. I will follow your recommendations.
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