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Error: Copper island connected to pads/vias detected

ziomau10

Hi,

I am using a switching component, and the suggested footprint contains several thermal vias/pads.

In my board an internal layer is connected to GND, and due to the distance between vias, some relief connection is blocked.

During the rules check I receive some errors of type: "Isolated copper: Split Plane  (GND)  on Internal Plane 1. Copper island connected to pads/vias detected. Copper area is : 0.12 sq. mils"

Actually the internal plane is like the attached image, and I cannot see any really isolated copper.

How is it possible to avoid this error and be able to generate the gerber files?

Thank you very much.

Mau.

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  • 0

    Your probably not going to like this but I think the best answer is make a better footprint. Frankly, what you have there is a mess.

    You have 10 vias in very close proximity (what is the hole to hole clearance?) presumably to aid heat transfer. Yet you have thermal relief on those vias which is contradictory.

    Why are you using relief connect instead of solid connect?

  • 0 in reply to voltsandjolts

    I like your answer, really, but I need some more help ...

    The footprint is suggested by the component manufacturer and indicated in the data sheet, and I'd like to use it as it is indicated.

    The holes are 10mils and the minimum distance is about 34mils.

     

    You are right, the holes are there for heat dissipation, and you are again right that the fact that there are thermal reliefs looks contradictory.

    Let me explain:

    During soldering process under the component there is a ground pad that must be soldered. If too much heat is drained by the internal planes it is possible that the pad is not correctly welded, that's the reason for the thermal reliefs.

     

    Having said this, I can change the internal planes connection type to "direct connect", and fix the problem hoping for good soldering anyway.

     

    But in case I can't or simply don't want to change the connection style:

    - What can I do to fix this problem?

    - Is it possible to change the rules (relief distance, connection width, isolation distance) just for this component, or any change will affect the whole board anyway?

     

    Thank you for any help

    Regards.

    Mau.

  • 0 in reply to ziomau10

    If you are assembling the board in a reflow process then just use solid connect. That will solder fine because the whole board is heated.

     

    If you are assembling with hot air (or an iron - but that doesn't seem suitable for this), then you may have to compromise.

    The question becomes; how much heat transfer can you have and still be able to solder it? Thats the decision you have to make.

    To reduce heat transfer, the answer is not to use thermal relief but use solid connect with less vias.

    There is no point in having thermal vias with relief connection.

     

    Hope this helps.

  • 0 in reply to ziomau10

    Regarding having different connection styles. If your ground is made up of polygons then you can draw a polygon under the device, attach to GND, add it to a polygon class and then give it different rules.

  • 0 in reply to e14softwareuk

    That is a nice trick.

    I guess it is not possible to do the same thing for internal planes, other than converting them into a signal layer with a bunch of poligons ...