Actions
Forum Thread Details
  • State Not Answered
  • Locked Locked
  • Replies 2 replies
  • Subscribers 83 subscribers
  • Views 1416 views
  • Users 0 members are here
Related
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Error with routing via style design rule

julach

Hello everyone,

 

I would like to define different routing via styles for BGA routing.

I would like to create rule for multi-layer via, and for top layer to layer 1.

 

In the layer stack manager/ drill pairs, I have the different drill pairs I can use.

image

 

And when I go to the design rules / routing / routing via style and I try to create the rule, I have a pop-up error saying "some rules have incorrect definitions". When I hover the rule, I see "Expression1 invalid".

image

 

Did I miss something for doing this ? Would someone know why I have the error while when I try with a net name, it works.

 

Thank you,

Justine

Parents Reply Children
  • 0 in reply to julach

    In CircuitStudio the routing via style is intended more for declaring a via size limit specially for high power nets (example AC-mains) where you want certain nets to enforce large vias and pads to handle the current/power.  Then you would put those nets in a net class and make a rule to prevent making the vias too small.  Similarly, you would define a net class for high thermal nets and then make a polygon connect style rule for direct connection.

     

    In your case, I would ask yourself if you really need a separate routing via style rule for blind or buried vias?  I understand that, for example, you might want to allow special rules for blind microvias for a multilayer build up with laser drilled holes on outer layers to adjacent inner layers.  Or maybe you would want to allow smaller holes on the inner layers buried vias since the core is thin and still have a rule that enforces min drill size on fully through hole vias.  That kind of sophisticated high density interconnect is where CircuitStudio begins to be crippled vs Altium Designer.  As you stated, you want to allow small blind vias for the BGA but presumably disallow small vias for others.

     

    Sadly, I'm not sure there is a good solution.  You should possibly define a net class and put the certain BGA nets into it.  Then base the rule on the net class.  I agree, these drill pair selections warning/error in the rules definitions should not be there if they truly generate invalid rules.

     

    Summary: these rules don't work completely CircuitStudio like they do on Altium Designer.  And there are bugs in menu selections.  The rules wizard is interesting and frustrating to play with as it shows some of the things you cannot do in CS that can be done in AD.

     

    But this brings up an interesting thing to try in the new release beta version and I think I'll have to see about it sometime this week.

     

    So, that all said, I worked with a sandbox board I have, and then made a rule based on drill pair to set the maximum hole size on a blind top to inner1 layer via to 8mil.  It says the rule selection criteria are invalid but I ignored the warning.  It did correctly find the violation if I made the via hole larger than 8 mil. and also if I made the pad violate the pad size for the via drill pair.  So, you might experiment with this a bit and let us know if warning it gives is the bug and the selection of drill pairs works or if the drill pairs based rules don't work.

     

    The report for rules gives me this. Says the scope is InDrillLayerPair('TopLayer - Inner Layer1'); that seems correct.

    image

     

    Thanks in advance for helping us understand this better.