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polygon region short circuit

acw210ee

So i have polygons overlapping each other connected to nets, it seemed to draw them fine with J1 in the pcb however i get the DRC i get a short errors:

Clearance Constraint (Gap=6mil) (All),(All)
Polygon Region (93 hole(s)) Bottom Layer Pad J1-1(2129.921mil,-459.134mil) Multi-Layer
Polygon Region (88 hole(s)) Signal Layer 2 Pad J1-1(2129.921mil,-459.134mil) Multi-Layer
Polygon Region (93 hole(s)) Bottom Layer Pad J1-3(1870.079mil,-459.134mil) Multi-Layer
Polygon Region (88 hole(s)) Signal Layer 2 Pad J1-3(1870.079mil,-459.134mil) Multi-Layer
Polygon Region (48 hole(s)) Top Layer Pad J1-3(1870.079mil,-459.134mil) Multi-Layer

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Short-Circuit Constraint (Allowed=No) (All),(All)
Polygon Region (93 hole(s)) Bottom Layer Pad J1-3(1870.079mil,-459.134mil) Multi-Layer
Polygon Region (88 hole(s)) Signal Layer 2 Pad J1-3(1870.079mil,-459.134mil) Multi-Layer
Polygon Region (48 hole(s)) Top Layer Pad J1-3(1870.079mil,-459.134mil) Multi-Layer

When i remove J1 the problem goes away, however i am not sure what is causing it. As the issue with the polygon pours does not occur with the ot

her components. Should i just ignore the issue?

image

Parents

  • As Shabaz said, DRC errors should not be ignored unless the reason is known and acknowledged. Which layers of your PCB have polygons on them and which nets are they connected to?

    Having 2 overlapping polygons on the same layer with different nets is generally a "no no". If you have to have polygons on the same layer with different nets, they shouldn't be overlapping.

  • in reply to GabeFromSpace

    Overlapping polygons is not a problem because when they are poured, they follow the design rules. My guess is that you need to repour the polygons.

Reply Children
  • in reply to charlieo21

    i did repour them. thats what is confusing. and going layer by layer i see nothing wrong

  • in reply to acw210ee

    Can you post a picture of J1 footprint?

  • in reply to acw210ee

    Can you check out the footprint in your library editor? If you temporarily delete the 5 pads is there anything underneath? Also, can you screenshots of the polygon pour settings for each of your problem polygons?

  • in reply to GabeFromSpace

    i got the footprint from the altium vault FP-PJ-047A-MFGFP-PJ-047A-MFG

  • in reply to acw210ee

    The footprint looks pretty normal. When you double-click on the polygon, what does the Polygon Pour window look like?

  • in reply to acw210ee

    At this stage you may as well start inspecting the Gerber files to see if the anomaly can be spotted.

    Could it be the thing shown below? The trace indicated with the orange arrow,seems to be on an inner layer. However, it is touching the light-grey shaded area indicated with the yellow arrow. 

    The light-grey area may be silkscreen perhaps, but if underneath that there is red pad, then that red pad copper will be on every inner layer. If this is the case it will be easy to see in the Gerber content. Or, perhaps you could switch off the silkscreen layers, to see where that red pad extends to. The component footprint isn't very good if the silkscreen is touching or overlapping the red pad. It should be a small distance away. It's not even needed to surround a through-hole pad, I don't see the point of that.

    image

  • in reply to acw210ee

     image

    I think this might be an error with circuit studio. As when i move the copper plane away like this the drc errors go away (you can see the polygons are still overlapping on other parts of the pcb and i get no DRC error). However when i move that copper polygon (which is connected to ground) back over J1 the errors come back for pin 3 (no connect) and pin 1 (12V).

  • in reply to shabaz

    The trace indicated by the orange arrow is on a mechanical layer and shouldn't interact with the Short circuit part of the DRC. It's meant for the design stage and shouldn't show up in the gerbers. the light gray area is a multi-layer pad, meaning it's a pad on the top, inner, and bottom layers. The red pad is a *hopefully plated slot. The silkscreen is the lighted traces on the footprint. That being said, exporting a gerber file and opening it up in a separate viewer like Gerbview would be a good idea at this point.

  • in reply to shabaz

    The DRC errors points to pads 1 & 3, apparently the GND polygon is touching those pads.

     try closing CS, opening again, repour all the polygons, run DRC again.

  • in reply to shabaz

    i looked at those traces and those are on the "top overlay" in the pcb footprint. whats interesting is i get no error for pin 5 when i do the drc only pins 1 and 3