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Altium CircuitStudio Forum polygon region short circuit
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polygon region short circuit

acw210ee
acw210ee over 2 years ago

So i have polygons overlapping each other connected to nets, it seemed to draw them fine with J1 in the pcb however i get the DRC i get a short errors:

Clearance Constraint (Gap=6mil) (All),(All)
Polygon Region (93 hole(s)) Bottom Layer Pad J1-1(2129.921mil,-459.134mil) Multi-Layer
Polygon Region (88 hole(s)) Signal Layer 2 Pad J1-1(2129.921mil,-459.134mil) Multi-Layer
Polygon Region (93 hole(s)) Bottom Layer Pad J1-3(1870.079mil,-459.134mil) Multi-Layer
Polygon Region (88 hole(s)) Signal Layer 2 Pad J1-3(1870.079mil,-459.134mil) Multi-Layer
Polygon Region (48 hole(s)) Top Layer Pad J1-3(1870.079mil,-459.134mil) Multi-Layer


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Short-Circuit Constraint (Allowed=No) (All),(All)
Polygon Region (93 hole(s)) Bottom Layer Pad J1-3(1870.079mil,-459.134mil) Multi-Layer
Polygon Region (88 hole(s)) Signal Layer 2 Pad J1-3(1870.079mil,-459.134mil) Multi-Layer
Polygon Region (48 hole(s)) Top Layer Pad J1-3(1870.079mil,-459.134mil) Multi-Layer

When i remove J1 the problem goes away, however i am not sure what is causing it. As the issue with the polygon pours does not occur with the ot

her components. Should i just ignore the issue?

image

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  • shabaz
    shabaz over 2 years ago

    Hi,

    The answer is no. A DRC error should never be ignored unless the reason for it is known and either corrected or acknowledged. In your case, since the reason is not known, it is not reasonable to ignore it.

    I don't use Circuit Studio (KiCad is better supported even through community support), so I'm not 100% sure of the reason.

    image

    What are all the small red circles? Are they the way Circuit Studio indicates an error, or are they very small top layer circular pads? If they are pads, they are exceedingly small. 

    Circuit Studio may use the concept of polygon 'priority' or 'rank' (other CAD packages do). It may be worth altering such a priority in case that is somehow causing a short.

    One more thing worth doing sometimes is to proceed with generating Gerber files, and then inspecting them in a Gerber viewer. Sometimes the problem area can be more easily identified from there.

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  • acw210ee
    acw210ee over 2 years ago

    the red pads do not exist and those are circuit studio error markings

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  • GabeFromSpace
    GabeFromSpace over 2 years ago

    As Shabaz said, DRC errors should not be ignored unless the reason is known and acknowledged. Which layers of your PCB have polygons on them and which nets are they connected to?

    Having 2 overlapping polygons on the same layer with different nets is generally a "no no". If you have to have polygons on the same layer with different nets, they shouldn't be overlapping.

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  • charlieo21
    charlieo21 over 2 years ago in reply to GabeFromSpace

    Overlapping polygons is not a problem because when they are poured, they follow the design rules. My guess is that you need to repour the polygons.

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  • acw210ee
    acw210ee over 2 years ago in reply to charlieo21

    i did repour them. thats what is confusing. and going layer by layer i see nothing wrong

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  • charlieo21
    charlieo21 over 2 years ago in reply to acw210ee

    Can you post a picture of J1 footprint?

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  • GabeFromSpace
    GabeFromSpace over 2 years ago in reply to acw210ee

    Can you check out the footprint in your library editor? If you temporarily delete the 5 pads is there anything underneath? Also, can you screenshots of the polygon pour settings for each of your problem polygons?

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  • acw210ee
    acw210ee over 2 years ago in reply to GabeFromSpace

    i got the footprint from the altium vault FP-PJ-047A-MFGFP-PJ-047A-MFG

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  • GabeFromSpace
    GabeFromSpace over 2 years ago in reply to acw210ee

    The footprint looks pretty normal. When you double-click on the polygon, what does the Polygon Pour window look like?

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  • shabaz
    shabaz over 2 years ago in reply to acw210ee

    At this stage you may as well start inspecting the Gerber files to see if the anomaly can be spotted.

    Could it be the thing shown below? The trace indicated with the orange arrow,seems to be on an inner layer. However, it is touching the light-grey shaded area indicated with the yellow arrow. 

    The light-grey area may be silkscreen perhaps, but if underneath that there is red pad, then that red pad copper will be on every inner layer. If this is the case it will be easy to see in the Gerber content. Or, perhaps you could switch off the silkscreen layers, to see where that red pad extends to. The component footprint isn't very good if the silkscreen is touching or overlapping the red pad. It should be a small distance away. It's not even needed to surround a through-hole pad, I don't see the point of that.

    image

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