Hi!
Routed length calculation is wrong (vias height does not taken into account).
CS version is 1.4.1 build 99.
When it will be fixed ?
Thanks!
Hi!
Routed length calculation is wrong (vias height does not taken into account).
CS version is 1.4.1 build 99.
When it will be fixed ?
Thanks!
To match a diff pair you should be using the same number of vias in _P and _N and thus via length is of no consequence.
Thanks for the reply.
Sure! This is just an example.
Real problem is observed when I need to match differential pair length to data bus as well as route all signals inside data bus.
In that case, you will need to manually add up via lengths which is non-trivial for more complex stack-ups. Or pony up several thousand dollars and upgrade to Designer.
Altium decided to leave the via length feature out of CS, which seems fair enough to me for its target market and cost.
Are you seriously ?
If so, I'm can't agree with you.
When we are talking about trace matching tool, yes, this is a "feature" available in more expensive package.
But when net length is showed without simple distance between layers this is just a "bug".
Yes, absolutely serious.
The target market for CS is where via length is unimportant or is at least trivial to manually calculate.
How many hundred MHz is your design operating at and who are you using to manufacture your controlled impedance boards? Doesn't sound like entry level PCB design to me.
Good product should have balance of available features.
CS has net classes, diff pair routing, multilayer stack-up, but on other hand simple via length does not automatically calculated.
More expensive products like Altium have much more other usefull features.
Via length is not feature nowadays. It is one of "must have" options today.
Hi,
a.stepanov has a good point.
CircuitStudio was marketed as a tool for professionals, isn't it? What's the point in buying a software tool if what you are saying is that the resulted PCB should be on the level with those drawn by hand on, let's say Inkscape?
Showing incomplete data seems a bug for me, too, regardless of the complexity of the design. Either you show it correctly or don't do it at all, otherwise it's misleading.
A "must have" for high frequency controlled impedance designs, yes.
But you're not actually using controlled impedance boards, are you? In which case your via lengths don't mean diddly-squat.
A "must have" for high frequency controlled impedance designs, yes.
But you're not actually using controlled impedance boards, are you? In which case your via lengths don't mean diddly-squat.