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Nets in hierarchy, what's equivalent of Room function in AD18, without copy / paste in layout, multiple channels

johnkimura

Considering CS, project involves duplicating analog and analog/digital circuits in the form of channels, 144 times.

 

Never used CS or Altium.  Past environments: PADS, Ultiboard, and Pulsonix.

 

Looking for explanation of how CS handles nets between sheets/blocks.

 

How many layers of sheets within sheets are possible?  Do net names through ports passing from lower to higher sheets carry as part of connection, local names? if not, how?  Altium appears to have local, global, and automatic naming with connection history.  How does CS handle?

 

What's most efficient way to layout, circuit from a single sheet, and then using same layout place copy onto pcb while preserving net names?

 

Altium provides rooms for circuits from schematic, layout, and then placing copies in the room.

 

A method has been proposed via cut and paste.  A more efficient approach would save time for designers of multi-channel devices.

 

 

https://www.youtube.com/watch?v=1VOOqheRauU

 

If not available, is the room function on the list for future releases? if so when?  Should be easy to port code from Altium Designer.

 

Thanks

 

John

  • That's a great video and is probably the very best way you can achieve a multi channel PCB layout. There are no rooms in CS, if you really need this functionality then best option is to consider Altium Designer, obviously a time/convenience/money trade-off.

     

    For schematics, in general net labels are local and do not go beyond the one sheet. Using the same local net label on different sheets refers to different nets, the names are local to the sheet. Ports are used to connect from one sheet to another, be it a multi sheet design or hierarchy. Global nets, such as power, are available to all sheets and reference the same net in all cases.

  • in reply to e14softwareuk

    Port to port or port to part pin nets, does CS provide names of the local nets inside the sheet?  This is helpful reading designs based on multi-sheet and hiearchy.

  • in reply to johnkimura

    I think the simple answer to your question is no, auto generated local net names do not show up on the schematic. One way to figure out the net name is to cross probe with the PCB where all nets are assigned a final name that can be easily seen.