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PCB Blogs Scrutinize my FPGA PCB Layout
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  • Author Author: shabaz
  • Date Created: 12 Jul 2022 3:23 PM Date Created
  • Views 6296 views
  • Likes 12 likes
  • Comments 33 comments
  • bga
  • pcb
  • fpga
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Scrutinize my FPGA PCB Layout

shabaz
shabaz
12 Jul 2022


Since cstanton alerted everyone to the PCB Forum, I thought I’d make use of it and try to get some help.

I’ve never done a ball grid array (BGA) layout, and I wished to have an FPGA board that I’d created myself, for some experimentation and general FPGA learning.

I’m planning to create a board using a Lattice Semiconductor part, because it is available in a sensible TQFP package which I am comfortable with. However, I thought I’d also give a Xilinx part a shot too, but it’s only offered in physically smaller packages; the simplest of which is what Xilinx calls an FTGB196 package. The part I’m using is Xilinx XC7S15 (PDF data sheet overview). However, since I've started the design, the chip is unobtainable! nevertheless, I thought it would be still useful to continue the design, and build it when the parts become available again.

image

The balls are spaced 1.0 mm apart, so it’s perhaps as friendly as such a type of package can get, I guess. I wish to use this with a 4-layer board, using low-cost PCB services from China.

I’ve gone with the following pad dimensions:

image

Here is each layer of the board, in the FPGA region.

image

This is what the board currently looks like zoomed-out(ground plane not shown), everything is still in the process of being routed, but basically I’m using layer 2 for ground plane, and layer 3 has some power planes.

image

Top and bottom layers (red and blue respectively) are for signal traces, and for all DC-DC converter traces, so I’ll use lots of vias when I pass the power to the power plane layer.

This is what the traces look like underneath the FPGA:

image

I need three supply voltages, and I’ve routed the DC-DC converter sections as visible in the screenshot above, but they still need to be positioned better. There is a basic power sequencing IC, not laid out on the PCB yet, it is LM3881, which too is now hard to obtain, but I have a few for now. Perhaps I can swap that out to a microcontroller if the LM3881 is inadequate, but it seemed fine. There's no JTAG programmer on-board; instead there will be a socket for the Xilinx programmer, just to keep things fairly minimal currently.

For additional memory, the FPGA is connected to a RAM chip (SRAM) on the right side. This is easier than DRAM. It’s messily routed currently.

I still need to route most of the signals in the IO banks; all that is done is the supplies, and the IO used for the SRAM.

Schematic

The schematics are incomplete, I still need to add connectors for the I/O. The project will be ported to KiCAD ideally (I started in EAGLE, but now I believe I can import it into KiCAD 6). The three sheets are shown below.

image

image

image

 

Anyway, that’s as far as I have got. Feel free to discuss/criticize etc : ) I’ll try to take on board any comments, however, I don’t want to re-do too much of it unless there’s a functional risk of it not working – for instance, some of the design admittedly looks anachronistic, like the massive DC-DC converters, and relatively physically large SRAM chip, but I really didn’t want to use tiny package devices except where I have no choice, i.e. the FPGA. I’d rather make the rest of it as large and serviceable as possible.

Thanks for reading!

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Top Comments

  • Jan Cumps
    Jan Cumps over 3 years ago +1
    Checking if rachaelp can chime in. She's been doing FPGA design and BGA fanout as a job.
  • wolfgangfriedrich
    wolfgangfriedrich over 3 years ago in reply to shabaz +1
    Hello shabaz, Thanks for the updated info. to see which I/O Vivado preferred, and then played with moving some around in the pin assignment file to see if Vivado was still ok with them, because I…
  • wolfgangfriedrich
    wolfgangfriedrich over 3 years ago in reply to shabaz

    Yeah, good catch. It is not strictly necessary for chip where the P&P can see the pins, but if there is room for the fids, it does not hurt. 

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  • shabaz
    shabaz over 3 years ago in reply to jc2048

    Hi Jon,

    Thanks for the photos! I will rotate the SRAM part too, it looks neater routed like that.

    I notice the FPGA has got the pick&place fiducial marks right next to it as Wolfgang mentioned.

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  • jc2048
    jc2048 over 3 years ago

    Just remembered that my Lattice Brevia-2 dev board has an asynchronous SRAM on it. This is how they've done it, in case you're interested ('they' being a 3rd-party design company - it wasn't done by Lattice themselves).

    No termination resistors. They've placed the SRAM close to the side of the FPGA, so that the traces are short. As you can see, though, they have length-matched the traces. It's an IDT device with a min cycle time of 15ns (read or write), but I've got no idea what the cycle time actually being used is. I could put the demo back on it and scope some of the signals if you wanted.

    image

    image

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  • shabaz
    shabaz over 3 years ago in reply to michaelkellett

    Hi Michael,

    Thank you for this, it's great to see a real layout! Also, it's excellent to hear that it's OK to route as is convenient, rather than sticking too closely to what the software chose initially. That will clean up the traces a lot. I'm quite excited now to complete this board. It felt like a long shot to get anything working, but now I have a bit more confidence (at least, until I have the chip in my hand because soldering it will be a battle for another day!

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  • michaelkellett
    michaelkellett over 3 years ago

    Hello Shabaz,

    I've had good results using TQFP FPGAs (Lattice XP2) with both static ram and SDRAM. In neither case have I used length equalised tracks or terminating resistors.

    The SDRAM clock was 100MHz.

    In both cases I chose general purpose IO pins based exclusively on pcb routing convnenience.

    The pic is an example (from 2010) of a prototype pcb with a 208 pin TQFP connected to to asynchronous static ram chips.

    image

    Design rules were 0.15mm track and gap, 0.55mm vias with 0.2mm holes.

    The two inner power plane layers are not shown.

    The Spartan 7 has more routing resource than the Lattice XP2 (which is a very old design)

    Of course you would absolutely not get away with this with modern DDRAM with its fast clocks and the need to use specific pins on the chip to work with Xilinx's hard interface and IP.

    MK

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