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  • Author Author: shabaz
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Scrutinize my FPGA PCB Layout

shabaz


Since  alerted everyone to the PCB Forum, I thought I’d make use of it and try to get some help.

I’ve never done a ball grid array (BGA) layout, and I wished to have an FPGA board that I’d created myself, for some experimentation and general FPGA learning.

I’m planning to create a board using a Lattice Semiconductor part, because it is available in a sensible TQFP package which I am comfortable with. However, I thought I’d also give a Xilinx part a shot too, but it’s only offered in physically smaller packages; the simplest of which is what Xilinx calls an FTGB196 package. The part I’m using is Xilinx XC7S15 (PDF data sheet overview). However, since I've started the design, the chip is unobtainable! nevertheless, I thought it would be still useful to continue the design, and build it when the parts become available again.

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The balls are spaced 1.0 mm apart, so it’s perhaps as friendly as such a type of package can get, I guess. I wish to use this with a 4-layer board, using low-cost PCB services from China.

I’ve gone with the following pad dimensions:

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Here is each layer of the board, in the FPGA region.

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This is what the board currently looks like zoomed-out(ground plane not shown), everything is still in the process of being routed, but basically I’m using layer 2 for ground plane, and layer 3 has some power planes.

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Top and bottom layers (red and blue respectively) are for signal traces, and for all DC-DC converter traces, so I’ll use lots of vias when I pass the power to the power plane layer.

This is what the traces look like underneath the FPGA:

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I need three supply voltages, and I’ve routed the DC-DC converter sections as visible in the screenshot above, but they still need to be positioned better. There is a basic power sequencing IC, not laid out on the PCB yet, it is LM3881, which too is now hard to obtain, but I have a few for now. Perhaps I can swap that out to a microcontroller if the LM3881 is inadequate, but it seemed fine. There's no JTAG programmer on-board; instead there will be a socket for the Xilinx programmer, just to keep things fairly minimal currently.

For additional memory, the FPGA is connected to a RAM chip (SRAM) on the right side. This is easier than DRAM. It’s messily routed currently.

I still need to route most of the signals in the IO banks; all that is done is the supplies, and the IO used for the SRAM.

Schematic

The schematics are incomplete, I still need to add connectors for the I/O. The project will be ported to KiCAD ideally (I started in EAGLE, but now I believe I can import it into KiCAD 6). The three sheets are shown below.

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Anyway, that’s as far as I have got. Feel free to discuss/criticize etc : ) I’ll try to take on board any comments, however, I don’t want to re-do too much of it unless there’s a functional risk of it not working – for instance, some of the design admittedly looks anachronistic, like the massive DC-DC converters, and relatively physically large SRAM chip, but I really didn’t want to use tiny package devices except where I have no choice, i.e. the FPGA. I’d rather make the rest of it as large and serviceable as possible.

Thanks for reading!

  • in reply to cstanton

    Hi Christopher,

    On 2- and 4-layer boards there's no concrete rules, but since it's good to have a low-impedance ground plane for the circuit, one layer can end up for that, or sometimes it may be split into two if there are a couple of separate grounds for instance. Other than that,anything goes, so since the components are on the top layer, then signal traces are convenient on that layer too, and power traces, with supply decoupling capacitors where needed. With a 2-layer board, that may be sufficient, but sometimes the ground plane may need a few traces so there's no choice but to put them there. Also, since boards curve in one direction if there's too much copper on one side and too little on the other, it can help to have areas of a power plane (can be ground plane) on the top side too, to balance things out. With a 4-layer board, it's a similar thing, but now there's the opportunity to have signal traces on two layers if it's needed, and still have a layer or two for ground/power planes. Any planes are then ideally on layer 2 or 3, so that signals can be traced, cut if necessary, and patched, if they are on the top or bottom. I once had to repair a car ECU where a power signal was running on an inner plane, and it had shorted, it was really awkward, milling a recess through the top two layers only, to clear the short : ) With the 4-layer board, since it's composed of two boards glued together, I won't need to balance out any copper on the top and bottom, I can just do that on the two inner layers as the design nears completion. Sometimes if there are (say) three signal layers and one ground plane, then you will want to know if the ground plane is layer 2 or 3, because you can use it as one side of a transmission line for RF, and that requires knowing the distance between the two layers making up the transmission line to make the calculation of the impedance (like 50 ohm). Incidentally the layers are not identically spaced; the two inner sides are closer to each other, i.e. between layer 2 and 3 there is (say) a tenth of the separation compared to between layer 1 and 2, and layer 3 and 4. They call that thin glue/insulating layer between the boards the 'prepreg layer'.

  • This looks very good so far.  That is a very ambitious project that you are taking on there.  The geometries are far beyond anything that I have attempted, not to mention the soldering job that you are looking at once you get the board.  Good luck!

  • Is it a typical convention to use certain layers for particular functions? Such as layer 2 is the ground plane, 3 for power, etc.?