Group Actions
Engagement
  • Author Author: shabaz
  • Date Created: Date Created
  • Views 6866 views
  • Likes 12 likes
  • Comments 33 comments
Related
Recommended

Scrutinize my FPGA PCB Layout

shabaz


Since  alerted everyone to the PCB Forum, I thought I’d make use of it and try to get some help.

I’ve never done a ball grid array (BGA) layout, and I wished to have an FPGA board that I’d created myself, for some experimentation and general FPGA learning.

I’m planning to create a board using a Lattice Semiconductor part, because it is available in a sensible TQFP package which I am comfortable with. However, I thought I’d also give a Xilinx part a shot too, but it’s only offered in physically smaller packages; the simplest of which is what Xilinx calls an FTGB196 package. The part I’m using is Xilinx XC7S15 (PDF data sheet overview). However, since I've started the design, the chip is unobtainable! nevertheless, I thought it would be still useful to continue the design, and build it when the parts become available again.

image

The balls are spaced 1.0 mm apart, so it’s perhaps as friendly as such a type of package can get, I guess. I wish to use this with a 4-layer board, using low-cost PCB services from China.

I’ve gone with the following pad dimensions:

image

Here is each layer of the board, in the FPGA region.

image

This is what the board currently looks like zoomed-out(ground plane not shown), everything is still in the process of being routed, but basically I’m using layer 2 for ground plane, and layer 3 has some power planes.

image

Top and bottom layers (red and blue respectively) are for signal traces, and for all DC-DC converter traces, so I’ll use lots of vias when I pass the power to the power plane layer.

This is what the traces look like underneath the FPGA:

image

I need three supply voltages, and I’ve routed the DC-DC converter sections as visible in the screenshot above, but they still need to be positioned better. There is a basic power sequencing IC, not laid out on the PCB yet, it is LM3881, which too is now hard to obtain, but I have a few for now. Perhaps I can swap that out to a microcontroller if the LM3881 is inadequate, but it seemed fine. There's no JTAG programmer on-board; instead there will be a socket for the Xilinx programmer, just to keep things fairly minimal currently.

For additional memory, the FPGA is connected to a RAM chip (SRAM) on the right side. This is easier than DRAM. It’s messily routed currently.

I still need to route most of the signals in the IO banks; all that is done is the supplies, and the IO used for the SRAM.

Schematic

The schematics are incomplete, I still need to add connectors for the I/O. The project will be ported to KiCAD ideally (I started in EAGLE, but now I believe I can import it into KiCAD 6). The three sheets are shown below.

image

image

image

 

Anyway, that’s as far as I have got. Feel free to discuss/criticize etc : ) I’ll try to take on board any comments, however, I don’t want to re-do too much of it unless there’s a functional risk of it not working – for instance, some of the design admittedly looks anachronistic, like the massive DC-DC converters, and relatively physically large SRAM chip, but I really didn’t want to use tiny package devices except where I have no choice, i.e. the FPGA. I’d rather make the rest of it as large and serviceable as possible.

Thanks for reading!

  • Checking if can chime in. She's been doing FPGA design and BGA fanout as a job.

  • in reply to Andrew J

    Hi Andrew,

    Thanks for checking it out, and the feedback! Good point on the heatsinks and leaving clearance for them. I could easily place screw-holes, since I've not routed so much so far.

    I have a reflow oven, but good point that it could be an opportunity to get it assembled. I'll think about that closer to the time.

    I only drew a box of ground plane around the FPGA just to show something, because I don't have a board outline yet to follow, but that will be across the entire board, and I plan to repeat on layer 3 too (except for where the power planes are under the FPGA) so both will be at 0V mostly as you say. I've tried to place the decoupling capacitors very close to where they are needed, underneath the FPGA, I had to go down to 0402 size there to squeeze them in. There's a Xilinx doc that lists the amount of decoupling required for their different FPGAs, so I followed that list. The SRAM can be clocked slower if there is an issue, but it would be nice to have reasonable performance. Although people usually use SRAM for high performance, I'm instead really using it for a simpler board layout, since probably everything below DDR4 is obsolete.

  • SparkFun wrote an interesting article on how they laid out an 81 ball BGA (Artemis) in 4 layers, including all the "rules" they followed:

    https://www.sparkfun.com/news/3122?_ga=2.220878495.625515125.1657666606-595437000.1657666606

  • Can I assume the FPGA / SRAM signals are going to be high frequency? Those signals are going to have a return path that follows the trace so you’ll need to be careful with the ground plane by those traces, with vias to the ground plane by the trace.  At high frequency, cross-talk between closely routed signal traces may become an issue.  I seem to recall there were some good YT videos by Altium and Robert Lefranc (?? That doesn’t sound right but I can’t remember his surname but he will come up if you search for PCB layout.)  having a ground plane on both inside layers helps because it minimises the distance between a trace and its return path (the pre-preg between layers 2 and 3 is relatively thick)  Obviously there’s going to have to be some compromise given the power planes for the FPGA: if you could minimise their size and use traces on the top/bottom layer to reach them it might help. I’d say layout of those two components, with decoupling caps, are the most important on the board but I’m guessing you already know that.

    I have no soldering advice for the BGA unfortunately.  I guess a reflow oven would help.  Alternatively, if your not fussed about practicing your soldering technique on that part, you might be able to get the board fabricator to do it if you can get the part to them.  

    Don’t forget that the FPGA (and possibly SRAM??) is likely to need a heatsink.  I’d guess that will go on top so do the calcs and leave enough clearance and maybe even mechanical support.

  • in reply to genebren

    Hi Gene, 

    Thanks! Such a chip will be new for me, I'm definitely not looking forward to assembling this!

    I've had to solder small modules with pads on the undersides only (i.e. like a BGA without the balls), but the pads were significantly larger, and my success rate was 33% with that so I definitely need to up my game.