High speed signals require impedance matching. Basically this means that the signal path must have a continuos impedance throughout which is matched with the receiver impedance. This is to prevent signal reflections that can corrupt the signal. In very basic language, the PCB track characteristic impedance depends on the track width, track copper height, distance from the reference GND plane and dielectric constant. Depending on the layer stackup, the user can calculate a track width to get target impedance in the CAD tool. This topic is clear to me.
Now lets come to vias. There are several issues with vias. Via is a 90 deg turn in signal path. Via geometry means that the signal path is different from a PCB track. Via does not have a reference plane by default. The geometry and lack of reference plane means that the via impedance will usually be not matched with the PCB track. This can lead to signal reflection and thus compromise the signal integrity.
Assume that we are doing PCB design for these: DDR3, DD4, PCIe gen 4 and the tracks.
So people that say via affect is small since its size is would be than wavelength. Some people say that we should put some stitiching vias nearby (don't know how far) and leave it at that and it should not cause massive problem.
It is not possible to completely avoid using vias. The basic question thus is as follows: when it is needed to use via, do we use any (small) size via and just hope that it works? Or do we need to design via with specific geometry and put a specific number of GND stitching vias close to it to give a return path for the current? Designing vias requires use of advanced tools which are called 3D solvers.
The question just aims to understand the correct approach to using via in high speed boards. Please note that I am an electronic engineer by profession, I have designed simpler PCBs in the past (2 - 4 layers) but not high speed stuff like DDR3 and transceivers. I am trying to gather the theoretical knowledge for high speed designs.
