Interesting "Competitors" for the Raspberry Pi

Got a quick email update from the Cubieboard folks ...

Intial 200 prototypes sold out. 1,000 users in the forum, 4,000 subscribed to the notification list, growing about 100 per day.

To meet demand they are crowd funding via http://www.indiegogo.com/cubieboard

Estimated shipping was end of Nov.

-J

Hey jamodio

I liked the sound of cubieboard's specs - so I just "contributed". It could be fun since I have several sata drives.

Peg

Oh! I see. I had misread, and thought each board had one processor. Agree, each 4-processor board could have a full-mesh (since there are lots of pins) (and they could still look like very fast virtual ethernet interfaces with some clever coding). The interconnect between boards - I can't think of good, cheap ways either : (

At some stage a dispatcher and FIFO to store up results would be pretty neat, and allow the 4x boards to

take tasks and process in their own time, and allow the base board to collect the results in its own time, but I guess would be extremely expensive to implement, with expensive FIFOs and probably some fast CPLD or FPGA.

I'm not very knowledgeable on multi-CPU designs.

shabaz wrote:

 

Oh! I see. I had misread, and thought each board had one processor.

Well, a single SoC on a modular board is already covered by Rhombus Tech , assuming that it sees the light of day.

However, that module is not intended for tightly coupled integration, because (AFAIK) DMA is not brought out on the EOMA-68 connector because they want to be able to switch SoCs as technology evolves, and DMA operation is not standard between manufacturers.  That is sensible of Rhombus Tech given their design target, but unfortunately it offers no opportunity for enhancing the SoC with DMA-operated links.

what about using an FPGA with a LVDS interconnect between boards or would that be more expensive than the gig switch?

George Ioakimedes wrote:

 

what about using an FPGA with a LVDS interconnect between boards or would that be more expensive than the gig switch?

That's probably the cheapest way to do it, and probably necessary both for signal robustness and to avoid radiating from here to China.

A TI SN75LVDS387 provides 16 x 630Mbps LVDS drivers for £8.01, so it's not prohibitive to have two of them for the 4x4 bidirectional links, driven by the FPGA which will need to handle message transfer through the drivers and DMA interfacing with the SoC.  I've not investigated further though.

This would not be a simple project.

and i'm fortunate to get favorable pricing from TI since we tend to buy a bunch of their stuff. so did you already jump ahead in the design cycle and are thinking about another board (the low cost i.MX6 competitor to RPi) or are your thoughts that this is a better product to produce?

No no, it would be an unmarketable product to produce, far too niche. 

I suspect that only researchers in parallelism would be interested in such special interconnect, everyone else wants one Ethernet per host.  Even the single 4-SoC board is likely to appeal only for DNS round-robin web serving and hence most purchasers would be expecting one Ethernet per host.

I think what I'm describing is what ARM should be knocking up in their R&D lab in order to determine what route to take for ARM clustering.  I doubt that a user-level product implementing similar concepts would be anything like the above in terms of actual implementation.  It's more an engineer's prototyping platform.

Stick with your first idea of a barebones i.MX6 RPI price competitor, I don't think you can lose with that.

In other words, this continues to be just "thinking aloud", although of course I'd love everyone's input to help it along.

At the very least this is tempting me to grab a couple of small FPGAs and LVDS drivers and experiment with message passing.  Since it'll have to be asynchronous and rate-adaptive, that's quite enough to chew on for a while.

OK, so the low cost i.MX6 will continue, hopefully I'll get a meeting with Freescale early this week and can update more after that. Still would be nice to have a bullet list of questions/requests that I can present to them.

I think the FPGA/LVDS is a decent enough approach to at least look into more. I haven't done any FPGA work but I go interested enough to buy a few development boards, all Xilinx so hopefully if things progress it can go with a Xilinx based solution.

Morgaine Dinova wrote:

 

George Ioakimedes wrote:

 

what about using an FPGA with a LVDS interconnect between boards or would that be more expensive than the gig switch?

 

That's probably the cheapest way to do it, and probably necessary both for signal robustness and to avoid radiating from here to China.

 

A TI SN75LVDS387 provides 16 x 630Mbps LVDS drivers for £8.01, so it's not prohibitive to have two of them for the 4x4 bidirectional links, driven by the FPGA which will need to handle message transfer through the drivers and DMA interfacing with the SoC.  I've not investigated further though.

 

This would not be a simple project.

PCI express might be a decent way to do it.  PCIe is IMO a decent compromise between message passing and shared memory.  There are a lot of inexpensive SoCs with PCIe.  Unfortunately, I haven't seen an inexpensive FPGA that supports PCIe.  For example, the smallest Xilinx Spartan-6 with built-in PCIe PHY and link layer is the XC6SLX25T which costs approx US$50 quantity 1.  I guess they assume that if you're using PCIe then you must need more logic, but more likely it's just ROI.

I don't know what the current cost is for PCIe routing chips.  PCIe is pretty nice point-to-point, but I don't know how well it scales.  PCIe is awfully fast at the PHY and byte level, so you really want dedicated hardware for those.

John Beetem wrote:

 

PCI express might be a decent way to do it.  PCIe is IMO a decent compromise between message passing and shared memory.  There are a lot of inexpensive SoCs with PCIe.  Unfortunately, I haven't seen an inexpensive FPGA that supports PCIe.  For example, the smallest Xilinx Spartan-6 with built-in PCIe PHY and link layer is the XC6SLX25T which costs approx US$50 quantity 1.  I guess they assume that if you're using PCIe then you must need more logic, but more likely it's just ROI.

 

I don't know what the current cost is for PCIe routing chips.  PCIe is pretty nice point-to-point, but I don't know how well it scales.  PCIe is awfully fast at the PHY and byte level, so you really want dedicated hardware for those.

As you say, PCIe is certainly fast.  From http://en.wikipedia.org/wiki/PCIe, per 1X lane in each direction:

• PCIe v1.x: 250 MB/s (2.5 GT/s)
• PCIe v2.x: 500 MB/s (5 GT/s)
• PCIe v3.0: 1 GB/s (8 GT/s)
• PCIe v4.0: 2 GB/s (16 GT/s)

In fact, it's so fast that my gut feeling says it's unlikely that ARM's DMA can keep up with single-lane transfers at max PCIe 2.x rate (500 MB/s after deserializing),  because that's average DDR2 SDRAM speed, and it's unlikely that DMA is served at anything like the full memory bandwidth.

While it's extremely tempting to use an existing standard, PCIe is an enormously large sledgehammer for this.  Perhaps smaller hammers can be found.

John Beetem wrote:

 

PCI express might be a decent way to do it.  PCIe is IMO a decent compromise between message passing and shared memory.  There are a lot of inexpensive SoCs with PCIe.  Unfortunately, I haven't seen an inexpensive FPGA that supports PCIe.  For example, the smallest Xilinx Spartan-6 with built-in PCIe PHY and link layer is the XC6SLX25T which costs approx US$50 quantity 1.  I guess they assume that if you're using PCIe then you must need more logic, but more likely it's just ROI.

 

I don't know what the current cost is for PCIe routing chips.  PCIe is pretty nice point-to-point, but I don't know how well it scales.  PCIe is awfully fast at the PHY and byte level, so you really want dedicated hardware for those.

As you say, PCIe is certainly fast.  From http://en.wikipedia.org/wiki/PCIe, per 1X lane in each direction:

• PCIe v1.x: 250 MB/s (2.5 GT/s)
• PCIe v2.x: 500 MB/s (5 GT/s)
• PCIe v3.0: 1 GB/s (8 GT/s)
• PCIe v4.0: 2 GB/s (16 GT/s)

In fact, it's so fast that my gut feeling says it's unlikely that ARM's DMA can keep up with single-lane transfers at max PCIe 2.x rate (500 MB/s after deserializing),  because that's average DDR2 SDRAM speed, and it's unlikely that DMA is served at anything like the full memory bandwidth.

While it's extremely tempting to use an existing standard, PCIe is an enormously large sledgehammer for this.  Perhaps smaller hammers can be found.