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Clarification of usable SPDIF modes

matwillis

I have been looking at the Wolfson card, specifically the Digital IO (SPDIF) functionality.

 

Having had problems attempting to use the card in 'External loopback' (i.e. SPDIF Output connected to Input), to test my temp fix for the Coherant DMA problems, I thought I would document my findings here (or to encourage others to shout, if I am wrong).

 

1. The SPDIF interface will work as a  simplex Transmitter -  the required frequency will be set from ALSA etc, and internal PLL will be configured correctly.

 

2. The SPDIF interface will work as a simplex Receiver -

 

3. The card will NOT work if you want to set a fixed Tx sample rate and also receive data at that rate.

Reasoning: (Looking at the datasheet, schematic and code) - When the wm8804 receiver is enabled, the internal PLL is configured automatically by the chip to lock to incoming data rate. The Transmitter is clocked from the internally generated (PLL) clock - no matter what the system sample rate is set to. Hence, you cannot say set the Transmitter frequency (e.g. to be 96kHz), and receive any data.

 

This means the card CANNOT be used;

a) as sample rate Master, if you want to receive data (even at the same, system frequency)

b) looping back it's output to input (e.g. for test)

 

(In theory, the WM8804 could be set into SLAVE mode, to use the MCLK pin as an INPUT. However, the datasheet suggests that Min 128Fs clock is required. Wiring across BCLK would not be fast enough. I cannot see where a 128Fs clock could be generated on the board. There is a DNP R43 that connects the WM8804 MCLK pin to GCLK (PIn7 of P1), but that seems to be the Master clock for the WM5102. )

 

4. The SPDIF interface can be used for Duplex Tx/Rx, iff it is a sample rate SLAVE to an external device.

 

Please comment if any of this is wrong. (I am about to stop my Wolfson Audio card ideas because of this).

 

Kind regards

Matt Willis

Oxford Creative Technology Ltd

  • Hi Matthew

    Thanks for the detailed analysis of the SPDIF capabilities.

     

    In summary I agree with your analysis and conclusions on the current operation of the audio card, let me add some additional detail which may help.

     

    Points 1 and 2 are essentially running the SPDIF Tx or Rx in isolation. In this case the audio card is master for Tx and slave for Rx. The reason the card is slave in Rx mode is to allow the clocking to adjust dependent on the clock rate of the SPDIF external device and synchronise the systems.

    Point 4 is when you want to have an external SPDIF input and also run the output at the same time. The use case here is that you want to lock to the external SPDIF source. This means the SPDIF Tx will operate at the same sample rate as the SPDIF input.

    The audio card architecture is to support options 1,2 and 4 with a fixed hardware configuration.

     

    Point 3 is limited by supporting options 1,2 and 4. As you point out for the audio card to support case 3 this would require a different clocking architecture.

    I understand your point for 3a, however if there is an SPDIF Rx then the Tx will output at the same frequency (just in case there is any confusion over runing the Tx and Rx at the same time). The difference here is that the sample rate master is the external Tx device. Therefore Tx and Rx can both operate but they will slave to the master sample rate of the external system.

     

    As a suggestion you can loop digital data within the WM5102 AIF to provide digital data back to the BCM device.

    If you can provide feedback on your use case and requirement for SPDIF loopback external to the card we could consider for the future.

  • in reply to Former Member

    Hi Scott

    Thanks for the confirmation.

     

    I was looking to use the Wolson card in a setup where I require Duplex Rx and Tx.

    The external devices I connect to either operate as 'Fs Clock Master' (RPi-WSP, as slave, Works OK), or 'Fs Slave' (RPi-WSP, as master, will not work).

     

    Having looked a bit deeper, there may be a solution for when the RPi-WSP is Fs master, but needs to Rx data. Your thoughts on my proposal would be good, before I spend time implementing.

    My proposed sw/hw tweaks would involve;

    1. Change the driver to run the WM8804 I2S/AIF interface as SLAVE to the WM5102 (in all cases), which changes WM8804 MCLK to become an input.

    (The current ALSA driver always has WM8804 I2S/AIF interface as MASTER to the WM5102 in all modes 1-4 above)

    2. The current setup already generates OPCLK (MCLK) on the Wolfson expansion header GPIO3. I would change the software (platform setup) to output this on GPIO4, which already goes through 1.8V to 3.3V level conversion. Then on the Wolfson board, WIRE GPIO4 (pin 15 of expansion header) to the WM8804 end of DNP R43. This means that WM8804 MCLK input is driven from OPCLK.

    3. In the driver where the WM5102 pll is configured,in the new situation when the RPi-WSP is Fs Master, simply keep the WM5102 PLL configured as the current Tx case (i.e. generating MCLK at fixed frequency, rather than locking to the external reference from the WM8804.).

    (The Rx path in the WM8804 should lock to the data, which will be at the same rate as WM8804 Tx data).

     

    Any thoughts?

     

    Matt

  • in reply to matwillis

    Hi Matt,

    It's great to see the engineering thought you have put into the solution you require. Although we have implemented a fixed implementation you are probably starting to see the options and configurations which is possible.

    From your proposal I believe you understand correctly what setup you need for the new use case, this is the WM8804 SPDIF Tx requires a clock source which is not linked to the WM8804 PLL when the Rx path is enabled. Therefore your idea to use the WM5102 clock output looks a good solution.

     

    Below are a few points which I thought might give you some help to make some minor changes to your proposed implementation.

    1. Suggest keeping the WM8804 AIF master for the existing supported SPDIF cases (see point 2).

    2. For the existing SPDIF cases the WM5102 uses the BCLK input as the clock reference and then uses the internal FLL to generate SYSCLK.

    3. For non SPDIF cases (i.e. WM5102 record / playback) the WM5102 uses the WM8804 CLKOUT as the input clock source.

    4. WM5102 GPIO3 is referenced to DBVDD3 (3.3V), so GPIO3 or GPIO4 could be used. 

     

    As you have indicated for this implementation to work the external device would need to be slave and ensure that the transmitted SPDIF signal from this source does not alter the clocking.

     

    Regards,

    Scott.

  • in reply to Former Member

    Hello,

    I'm a bit new to this board and to wm5102 so I have a question related to S/PDIF IO.

    I am using S/PDIF IO successfully with S/PDIF RX as master for the whole board. No problem, it works fine if I do some process in the rPi and work with same sample rate for I/O and rPi processes.

    But if I receive a S/PDIF digital stream at 44.1kHz and want to process at 96kHz on the rPi, I'm missing some infos.

    In that case, I need to have SYSCLK and ASYNCCLK working at different rates, and pass audio through ISRC and ASRC.

    Then I cannot find all needed commands, so my question is : where can I get the amixer commands to set SYSCLK, ASYNCCLK, SAMPLE_RATE_1, MCLK ???

    For now, I havent found yet the good names to set it through amixer commands. One that works is :

    amixer -q Dhw:sndrpiwsp cset name 'TX Source' S/PDIF RX

    but I need to dissociate SYSCLK and ASYNCCLK, especially the command to set SYSCLK to an internal fixed value.

    Thanks for any help.

    Jean-Luc