Thanks to BigG I was made aware of a feature in the RP2040's statemachines where the sideset value can be latched and doesn't need to be defined for every instruction.
Posting here, not to overhelm their amazing project. Taking an I2S pio program as an example:
@rp2.asm_pio(out_shiftdir=0, autopull=True, pull_thresh=32, out_init=[PIO.OUT_LOW],sideset_init=[PIO.OUT_LOW]*2,fifo_join=PIO.JOIN_TX)
def samplepio():
wrap_target()
label('entry')
set( x, 14) .side(0b11)
label('bitloop1')
out( pins, 1 ) .side(0b10)
jmp(x_dec, 'bitloop1') .side(0b11)
out( pins, 1) .side(0b00)
set( x, 14) .side(0b01)
label('bitloop0')
out( pins, 1) .side(0b00)
jmp( x_dec, 'bitloop0') .side(0b01)
out( pins, 1 ) .side(0b10)
wrap()
When I print out the assembled machine code for this pio routine using:
addr = 0
for instr in samplepio[0]:
bcode = '{:016b}'.format(instr)
print('{:02X}: {:} {:} {:}'.format(addr,bcode[0:3],bcode[3:6],bcode[6:]))
addr +=1
I get the following:
00: 111 110 0000101110 01: 011 100 0000000001 02: 000 110 0001000001 03: 011 000 0000000001 04: 111 010 0000101110 05: 011 000 0000000001 06: 000 010 0001000101 07: 011 100 0000000001
You can see only 2 bits are used for the sideset values.
If I comment out one sideset directive, then uPython automagically enables the sideset enable bit and the instructions now appear as:
00: 111 111 0000101110 01: 011 110 0000000001 02: 000 111 0001000001 03: 011 100 0000000001 04: 111 101 0000101110 05: 011 100 0000000001 06: 000 101 0001000101 07: 011 000 0000000001
I commented out the last sideset directive and you can see the presence of an enable/latch bit on all previous instructions.
Thanks to BigG, I learned something new!!!