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Raspberry Pi Pico 2 and a new micro-controller with RISC-V and Arm?

cstanton

image

I haven't made the jump to playing with RISC-V yet, I'm wondering what the advantages are there.

And this makes it quad-core, right?

Crazy.

I have a lot of reading to do!

 Hardware Design with the RP2350 /  RP2350 Datasheet /  RP2350 Product Brief 

 Of course there's the Pico 2:  Raspberry Pi Pico 2 Datasheet  - I admit I haven't touched a Pico 1 yet.

What am I missing out on?

Parents

  • I'm going to say it:

    Risk architecture (like many these days) only matters to 

    • controller manufacturers that have to pay a per-chip license to ARM, and
    • assembler language developers that do a better job than the GCC / Lang toolchain developers
  • in reply to Jan Cumps

    CPU architecture affect much more and one more reason is: perfromance. While for some embedded application it does not matter much, nowdays we see increased usage of AI/ML models on MCU and in that case perofrmance is very important and it really matter if your AI model run 5 times faster on the same clock rate just because instruction set is more optimized for these applications.

    I thought that vendors will go Maxim way that integrates HW accelerator and optimized DMA for accelerating loading data, coeficients, and do ccomputations in HW accelerated and highly paralelised way, but it seems that most other vendors go by increasing clock rate and optimizing instruction set (ARM Cortex-M35, 55, 85) for these applications instead.

Reply
  • in reply to Jan Cumps

    CPU architecture affect much more and one more reason is: perfromance. While for some embedded application it does not matter much, nowdays we see increased usage of AI/ML models on MCU and in that case perofrmance is very important and it really matter if your AI model run 5 times faster on the same clock rate just because instruction set is more optimized for these applications.

    I thought that vendors will go Maxim way that integrates HW accelerator and optimized DMA for accelerating loading data, coeficients, and do ccomputations in HW accelerated and highly paralelised way, but it seems that most other vendors go by increasing clock rate and optimizing instruction set (ARM Cortex-M35, 55, 85) for these applications instead.

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