Here I tried to learn different methods to program the Digilent ARTY Z7 Dev Board. One simple way is to program .vhdl file in the Vivado and then create the sdk. Another way is to create the Block diagram in the vivado and then export the hardware to the SK.
VHDL code program on ARTY Z7
Here I have a simple .vhdl code and I programmed the fpga.The aim is to light 4 leds by pushing the 4 buttons on the dev board. I also took the necessary part from GITHUB and wrote the constraints file .xdc
Writing appropriate .xdc file to manage the constraints
set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { b }]; #Sch=LED0
set_property -dict { PACKAGE_PIN P14
IOSTANDARD LVCMOS33 } [get_ports { c }]; #Sch=LED1
set_property -dict { PACKAGE_PIN N16
IOSTANDARD LVCMOS33 } [get_ports { x }]; #Sch=LED2
set_property -dict { PACKAGE_PIN M14
IOSTANDARD LVCMOS33 } [get_ports { z }]; #Sch=LED3
set_property -dict { PACKAGE_PIN D19
IOSTANDARD LVCMOS33 } [get_ports { a }]; #Sch=BTN0
set_property -dict { PACKAGE_PIN D20
IOSTANDARD LVCMOS33 } [get_ports { d }]; #Sch=BTN1
set_property -dict { PACKAGE_PIN L20
IOSTANDARD LVCMOS33 } [get_ports { y }]; #Sch=BTN2
set_property -dict { PACKAGE_PIN L19
IOSTANDARD LVCMOS33 } [get_ports { w }]; #Sch=BTN3
This error appeared many times after reset and sometimes during on. Then you must re-fresh the project and if not then re-power the board again. At some point I thought the board is broken. But it is not true the FPGA became very hot and after I left turned off for few hours it was running good again.
Another mistake I also made often is the programming jumper should be set correctly to JTAG-QSPI to program bitstream.
After re-starting the Vivado 2016
Looking at Implementation of the code on FPGA
Details in the timing report. Luckily no timing failures for this simple project. Else it must be checked here
Going deeper and looking into the Schematics created from the VHDL code
Programming the bit-stream file on fpga dev board.
Here the vivado SDK was not used to run the code on FPGA.
Vivado Block Diagram design to program ARTY Z7 FPGA
In this mini-project I did not write an fpga code but connected the leds and push buttons using the Block Diagram from Vivado and added as GPIOs. The control of the LEDs and push buttons in done in SDK software. The results I also sent in serial port TeraTERM to see which button was pushed for which led is ON. When using this approach the .xdc file (constraints file for the hardware on the fpga) may not be manually written.
Testing with the Vivado SDK 2016
LED, button and SW in VivadoSDK to program ARTY Z7 FPGA
Further the block diagram creation approach is used to control the push buttons, leds and the two switches on the FPGA board. The outputs of the on board switches are sent to Tera Term serial port to see the current status.
The Block Diagram implementation
After generating the bitstream, I exported the hardware to the Vivado SDK. And the control of the leds and push button is written in the SDK software using C language.
Finally programming the FPGA ARTY Z7 board from the Vivado SDK.
As seen I also had the issue when programming the VivadoSDK code on the Digilent Arty-Z7.
The AP transaction error, DAP status f0000021 error and Memory write error at 0x100000. AP transaction timeout are also common when programming the fpga.
The only work out on the Digilent forum as written is
- The boot mode jumper must be set to JTAG
- Press the PORB button for sometime, and only then Program FPGA.
- Re-Launch or re-program from VivadoSDK menu on the FPGA Hardware to work.
Top Comments