Genesys ZU: Zynq Ultrascale+ MPSoC Dev Board RoadTest

16 Jul 2020

A few days ago I received the Genesys ZU board to work with it and submit a RoadTest. This opportunity came right on time for me, as I have been particularly interested in Hardware Acceleration (Hardware Design for Multi-Modal Data Acquisition and Processing) and I was checking to purchase a platform in order to begin investigating, apply models, provide results, etc, exactly the same way you do when working with GPU based hardware acceleration but, implementing it on an FPGA instead. Therefore, in that context the Ultrascale+ platform was, for me, one of the main candidates.

Intro

The board arrived inside a big box and everything was really well packaged (including the board, a 100W power supply, a JTAG cable, usb cables and an sd card).

The Genesys ZU is based on the Xilinx Zynq UltraScale+ MPSoC Arm-FPGA hybrid, meaning that the SoC includes not only an FPGA, but also a Quad-core Arm Cortex-A53 (APU), a Dual-core Arm Cortex-R5 MPCore (RPU) and a Mali-400 MP2 (GPU) as hard processors inside the chip. It also features 4GB of DDR4 external RAM (upgradeable), a 256Mbit / 32Mbyte FLASH and an SD card reader. In terms of connectivity, there is a plethora of options like, 2.4GHz WiFi, 1G Ethernet and we can also connect a WWAN or a LoRa module via the mini-PCIe port. Through that specific port, we may also connect an SSD using and mSATA/mini-PCIe converter. Looking at the expansion ports we can find a single ZMOD Port (SYZYGY compatible), a FMC connector, four PMOD ports and two MIPI CSI-2 ports. Last but not least, there are plenty of User I/O (5 LED, 4 switch, 7 buttons).

I would like to highlight the ZMOD option, which is the Digilent's support for SYZYGY-compliant modules as an open standard and high-speed expansion port.

The above configuration is common for both the ZU-3EG (RoadTest) and ZU-5EV, where the latter has an extra 10G SFP+ port and two HDMI ports (SINK/SOURCE). Read more specs in the Reference Manual

The plan is to test PetaLinux programming as well as bare metal programming.

Before power on:

Check for the SD card already in the package and insert it in the sd card reader slot (J9). Ensure the power switch (SW5) is in the OFF position and connect the power supply to the ATX power connector (J41).

Ensure the JP3 header (programming/boot mode) has a jumper in the SD position

The included SD has the PetaLinux binaries pre-installed so, connecting the micro USB cable from UART (J8) to host computer, will provide access to system's terminal (115200-8N1).

Booting:

Now I am ready to put the SW5 to ON position and wait for the system to boot. I can access the terminal console via serial[1] or ethernet (user and password is root).

A quad core ARM processor and 4GB of ram are available (cpuinfo & meminfo):

Testing the OOB demo

Inside the Petalinux image there is also the OOB-os demo project which includes the zuca-test scripts to play with buttons, switches and leds, through linux. Ηere's a blink video and a snapshot:

uio-test:

DP-test: (tip: use a native DisplayPort cable end to end, as the DP-to-HDMI adapters doesn't work)

and the OOB-hw demo uploaded using Vivado:

Next step - Build a custom Hardware Design

High Performance Imaging is a well-documented and a very interesting project created by Adam Taylor which showcase the hardware capabilities of Zynq Ultrascale+ MPSoC processing system. It uses Digilent's Pcam 5C (also kindly offered for my roadtest) to tunnel an image stream to Display Port and it can be used as a base project for creating some more complex image processing systems (eg object detection, image segmentation, adding layers, etc).

It is a combined PS-PL design so, it includes a block diagram in Vivado and C application code in SDK. The complete project code can be imported from github and uploaded directly on the board. Check below a few screenshots during my test:

upload bitstream and application code via SDK:

debug messages on the console:

live video stream:

More project ideas to get you inspired:

Genesys ZU Vitis Acceleration Platform

Single Tone Detector with Genesys Z7 and RTU

DOOM with Hardware Accelerators on FPGA

Conclusion

Genesys ZU-3EG is an advanced platform combining processing power and programmable logic in a SoC. The board is fully eligible for Edge Computing and Hardware Accelerated projects by offering hardware and software co-design features. Thus, AI modeling and inference using Deep Neural Networks, Real-Time Vision and other algorithms for High Performance Computing can be realized inside a FPGA, introducing greater power efficiency than GPUs[3], exploiting frameworks like OpenCL and FASTCUDA[4] and facilitating dynamic reconfiguration.

Appendix:

[1] Boot console out disabled issue:

I experienced an issue with the serial console out, more specifically I could not fetch any data to minicom so, I tried to login via ssh, but the default user/pass (root/root) was also failing. After digging in the Xilinx forum, I found out that the dropbear ssh server had the root user login disabled by default. Therefore, I had to rebuild the the Petalinux image[2] in order to enable root login via ssh. With the new BOOT.bin created, I was able to login using ssh and check the system message on boot (dmesg) and this is how I identified that bootconsole was getting disabled:

To remediate the specific issue, I had to rebuild the image again, with the custom bootargs options. More specifically, I had to add the following lines (chosen) in ./project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi: