The TPS92512EVM-001TPS92512EVM-001 evaluation module (EVM) helps designers evaluate the operation and performance of the TPS92512HV buck switching regulator designed for high-current LED-drive applications. The TPS92512HV device is designed to control the drive of high-brightness light emitting diodes and features a wide input voltage range (4.5 V to 60 V), PWM dimming capability, analog dimming capability, adjustable/syncable switching frequency, and input undervoltage protection.
The board is clearly intended for use In a laboratory, so special attention has been paid to make all the inputs and outputs easily accessible and easily connectable to scope’s and function generator’s probe (take a look at the unique shape of the pins in the photo below, that are perfect to take the probe in place)
PIN CONNECTORS
Here is a description of the board’s connectors
J1, LED+, LED
The screw-down connector, J1, and the test posts marked LED+ and LED- are for connecting the LED load to the board. The leads to the LED load should be twisted and kept as short as possible to minimize voltage drop, inductance, and EMI transmission. This design is for approximately 2 to 7 white LEDs.
J2, VIN, GND
The screw-down connector, J2, and the test posts marked VIN and GND are for connecting the EVM to the DC input voltage supply. The input supply ground should be connected to J2 or the GND test post directly next to J2. One other GND test point is provided on the board that can also be used for all purposes but input power.
UVLO
The test point UVLO connects directly to the UVLO pin of the TPS92512 device. The voltage range is 0 V to 4.5 V if driven externally. The UVLO resistor divider should be used for the UVLO function, but the UVLO voltage can be monitored with this test point. Pulling UVLO to GND will also serve to disable the part and put it into low power shutdown mode.
PDIM
The PDIM test point connects directly to the PDIM pin of the TPS92512 device. Leave open for normal operation. If PWM dimming is used, apply a square wave with a low level of GND and a high level of between 2 V and 4.5 V. The dimming frequency range is 100 Hz to 1 kHz.
The TPS92512 incorporates a PWM dimming input pin, which directly controls the enable/disable state of the internal gate driver. When PDIM is low, the gate driver is disabled. The PDIM pin has a 1 µA pull-up current source, which creates a default ON state when the PDIM pin is floating. When PDIM goes low, the gate driver shuts off and the LED current quickly reduces to zero. A square wave of variable duty cycle should be used and should have a low level below 0.79 V and a high level of 1.45 V or above.
The TPS92512 uses a sample-and-hold switch on the error amplifier output. During the PDIM off-time the COMP voltage remains unchanged. Also, the error amplifier output is internally clamped low. These techniques help the system recover to its regulation duty cycle quickly. The dimming frequency range is 100 Hz to 1 kHz and the minimum duty cycle is only limited in cases where the BOOT capacitor can discharge below its under-voltage threshold of 2 V (VIN is within 2 V of the total output voltage).
SYNC
The SYNC test point is AC coupled to the RT/CLK pin of the TPS92512 device through a 4.02-kΩ resistor in series with a 470-pF capacitor. Apply a square wave with a low level of GND and a high level of 3.3 V to synchronize the switching frequency to the applied frequency. The frequency range of SYNC is 200 kHz to 2 MHz.
IADJ
The IADJ test point connects directly to the IADJ pin of the TPS92512 device. The default is pulled high through a 10M resistor to VIN resulting in an ISENSE voltage of 300mV. The range on the IADJ pin is 180 mV to 1.8 V and the corresponding ISENSE voltage is VIADJ / 6.
PH
A large via, labelled PH, is included and sized specifically to receive the probe tip of a standard 10x probe. Use this via to monitor the switching waveform at the PH pin of the device.
Even if most smartphones are equipped with a light sensor, this is absolutely not suitable for VLC applications, since its refresh rate is simply too slow. I installed a simple app (Sensor rate Checker, available for free in the PlayStore) on my Android smartphone and the result is that the maximum refresh rate for the light sensor is in the order of same Hz. Such a refresh rate would required the LED to switch on and off so slowly that the user would see an annoying flickering light.
To make the light emitted by LED as flicker-free as possible, it must switch at the frequency of some kHz. I can anticipate that to detect a signal that changes at that frequency, one can exploit the rolling shutter effect of the smartpones’ CMOS camera (more on that in the next posts)
That’s said, I need to decide which kind of modulation can be used to encode data. Despite there are many studies about schemes that use Quadrature Amplitude Modulation (QAM), Orthogonal Frequency Division Multiplexing (OFDM) and that are definitely out of my reach, I will use a very simple On-Off Keying technique. Basically I will transmit a logic “0” by pulsing the LED at a frequency f0 and a logic “1” by pulsing the LED at a different frequency f1. I Don’t know if this is going to be actually required, but probably a third frequency fp could be required to transmit a “preamble” that will make the smartphone able to detect the start of the frame
Since the maximum PWM frequency supported by the TPS92512 is 1 kHz, I will use the following frequencies
- fp = 500 Hz
- f0 = 750 Hz
- f1 = 1 kHz
Reading through the TPS92512 datasheet, it seems that there is lower limit to the PWM duty cycle. The TPS92512 evaluation board has been designed with the following requirements in mind
- VIN range of 12 V to 48 V
- UVLO set to 12 V with 0.8 V hysteresis
- 3 LED output, 9.7 V stack, VOUT = 10 V
- 1.5A LED current (at VISENSE = 300 mV for best accuracy)
- Switching frequency of 570 kHz
- LED current ripple of 10 mA or less
So a CBOOT of 0.1 uF has been selected
According to datasheet, the sink current of CBOOT is 1 mA, so we can calculate the maximum off time of the PWM signal
This means that the signal can stay off for no more than 0.2 ms per cycle. In the worst case (i.e. with the lowest frequency) this means that the PWM duty cycle must not be less than
