In Search of RoadTesters to Take On The All Programmable SoC (AVNET MiniZed RoadTest)

Randall, you missed a vital point.

11. Enjoy pounding your head against a wall while you search google for snippets of information to make your journey more pleasurable.

I've just been reading through the docs today and there is a lot to take in. Maybe too much.

The product itself seems to be nothing short of amazing (for the price), but the cost of entry from a knowledge based perspective is really steep..

Of course others may see it differently.  :-)

Robert,

Well, I think you make and excellent point. I would be willing to have you or someone roadtest this hypothesis: cost of entry from a knowledge based perspective...

I think this valuable to both developers would are considering the Zynq SoC AND the supplier Xilinx //Avnet. If the "cost of entry from a knowledge based perspective" is too steep, and you or another roadtester could identify where that is, perhaps the supplier could address the issue and re-deploy something to help. But, it needs to be tested.

Thanks for responding.

Randall

Hi Randall,

The issue Scott raised is why I have not applied.

With my ADD issues, I am not sure I can learn how to use the device in the time allotted.

Now if they really want someone who has the experience, but needs a very simple approach to using this device I would reconsider.  I do know a lot about these devices, so understanding what to do is not the problem.  I am stopped by the process of learning their software to do the implementation.

DAB

rscasny  wrote:

 

the "cost of entry from a knowledge based perspective" is too steep, and you or another roadtester could identify where that is, perhaps the supplier could address the issue and re-deploy something to help. But, it needs to be tested.

The thing is, these are very high-end devices - not the kind of thing you can just dabble with on the odd evening.

So the target audience for these things is people who have a serious project - and, therefore, a serious budget to spend serious time dedicated to learning the thing.

The suppliers do address this by providing FAE support, training, etc - but I guess that's not going to be included in the RoadTest ... ?

Don,

I appreciate your candor. I think you articulate the issue quite well. Our community has not focused on developing with the Zynq soc so there's going to be a learning curve.

I am considering adding 2 weeks to the testing period for coming up to speed on the tools.

I am also working on getting more tutorials of Vivado.

Thanks for your input.

Randall

Andy,

Thanks for pointing this out:

"the suppliers do address this by providing FAE support, training, etc - but I guess that's not going to be included in the RoadTest ... ?"

I haven't talk about this specifically with the supplier, but let me bring it up.

Randall

rscasny  wrote:

 

I am considering adding 2 weeks to the testing period for coming up to speed on the tools.

The thing is, it's going to take something like 2 full weeks of dedicated, 100% focus to get up to speed on something like this.

Now, that's fine if it's your day job and you have an immediate, specific project on which you're going to use it.

But, as a "sideline" - it's a big ask.

I certainly couldn't justify it.

EDIT

Just seen michaelwylie's comment below: https://www.element14.com/community/message/231847/l/re-in-search-of-roadtesters-to-take-on-the-all-programmable-soc-avn…  - saying, I think, essentially the same thing.

rscasny  wrote:

 

I am also working on getting more tutorials of Vivado.

I think this might be very useful to anyone participating.

especially if its taken from the entry level through to something moderately useful.

I watched some youtube z7000 videos on working with vivado and the level of complexity involved in the software is pretty daunting.

Even just to create a simple AND gate required the use of the multiple steps and varying stages as well as a third party website to help

generate some simulation code.  That to me just seems nightmarish to troubleshoot while you try and figure out what the hell you are doing.

My main takeaway from that was, that the vivado application wasn't the only part of the process that you had to become familiar with.

You had to learn other external tools as well.

In my opinion the roadtest for this one is a wolf in sheep's clothing. :-)  Its definitely a worthwhile challenge for someone that has

a significant portion of time to invest in learning the ins and outs of the board and the software infrastructure.

Once you tame that wolf though, you'll be able to do use its power to solve a multitude of design problems / projects.

@ Andy Neil, You are correct in principle but I think a bit light on the time needed - 2 weeks is nothing like enough !

@ Robert - There is  a load of tutorial stuff on Xilinx's website - I didn't have problems with getting information - just that there is so much of it - I think I've mentioned before that, for example, the documentation for the DDR3RAM controller runs to >650 pages - and that's just one tiny part of the chip. To understand this chip and the tools you need to skim thousands of pages of documentation and actually read quite a bit of it.

With regard to the miniZed, to get up and running with the Vivado toolset and get a an FPGA design communicating with the ARM and doing something useful - will take no less than 8 weeks (and that's if you are already a competent FPGA designer). Michael Wylie (above) said it took him three weeks with a similar Altera part to get to a blinking LED !

I've recently (Q1 this year) done the transition form Lattice tools to Xilinx Vivado and it was quite a big jump. Interestingly, I've just done a design (less ambitious) using Altera parts and tools and found the Altera tools a much easier step.

The point of all this is to manage expectations for this road test

In order to get this part or board to a simple useful design will take a skilled pro about £15k - £25k worth of their time - so you are either going to get some one who is kind enough to let you piggy back on an existing project, wait  a year while someone smart and gifted does it in spare time, or get a picture of the cardboard box and a screenshot of the pre-cooked demo running.

To try and put this in perspective - on our own Xilinx transition project (not to Zynq but just a biggish (200kLUT) FPGA) we bought  2 cheap and one less cheap dev board and made 2 custom dev boards. About 25 weeks of work to get to the stage where we can give the go ahead to take it to prototype.

MK

rscasny

"cost of entry from a knowledge based perspective"

I'm wondering if that (or some variation) shouldn't be part of the RT scoring.

Obviously some devices are much easier than others, and the supporting documents and programming software can vary the score.

Mark

rscasny

"cost of entry from a knowledge based perspective"

I'm wondering if that (or some variation) shouldn't be part of the RT scoring.

Obviously some devices are much easier than others, and the supporting documents and programming software can vary the score.

Mark