Summer of FPGAs -- Lattice MACHXO3L Starter Kit - Review

Table of contents

RoadTest: Summer of FPGAs -- Lattice MACHXO3LF Starter Kit

Author: skruglewicz

Creation date:

Evaluation Type: Development Boards & Tools

Did you receive all parts the manufacturer stated would be included in the package?: True

What other parts do you consider comparable to this product?: OrangeCrab Dev Board, XiLink Ultra96

What were the biggest problems encountered?: Getting the Lattice Programmer configured correctly to download the program to the board. I was trying to follow the tutorial for the board which is based on the LCMX03L which uses a different memory configuration (NVCM) . The board I received , the LCMX03LF contains Flash memory instead. When I figured it, out I was programming the board fine.

Detailed Review:

This RoadTest review will evaluate the embedded software Development capabilities of the Lattice Semiconductor.MachX03LF Starter Kit


This kit is an FPGA based Development board, that contains the Lattice FPGA part#: LCMXO3LF-6900C-5BG256C and allows for evaluation and development of MachX03LF FPGA designs. I will be focusing on the Lattice toolchains available (Lattice  Diamond IDE & Propel)  to conduct experiments using demo designs available on the Lattice Website. I will also be checking out how to get started programming the board. I will be evaluating how a novice Hobbyist like myself can experiment with developing solutions without much pain. I will attempt to lay out a "Roadmap for Beginners" of FPGA programming, while I learn it myself. I will not be touching on the History of or what an FPGA is, there are plenty of resources here on element14 and on the Web on this topic. I have also included some of my favorite references at the end of this review.


Up until now, I have been experimenting and performing reviews on MCU based Dev Boards, using IDE's and SDK's specific to the kit being used. I will attempt to do the same when reviewing this board. I am interested in the "Parallel" aspects of FPGA's  as opposed to "Sequential" properties of MCU based programming. I have done Assembler programming, but that was a long..long..long time ago on an 8 bit Z80 Microprocessor. I'm a Software engineer by trade and I'm intrigued by the concepts of experimenting with Software on a Chip (SoC) and experimenting with the implantation of proven hardware subsystems that have been etched in silicone. I'm eager to explore the "FP" in the acronym FPGA. The concept, of logic that had been etched permanently in silicone, but now to be able to "Field Program" it over and over again is mind blowing.


This is my second evaluation review of a FPGA based development kit. My other review Summer of FPGAs -- OrangeCrab Dev Bd - Review, contained the Lattice ECP5 FPGA chip. This board utilizes Open Source Toolchains for developing and implementing embedded software, which I was able to experiment with successfully. My hope at the time was to learn the Lattice toolchains, since the board contains the manufactures ECP5 FPGA.

I was not able to accomplish this at the time of the review, but I plan to return to it in the future. This was my first introduction to FPGA embedded software environments and the recommended toolchains by the manufacturer was to use Open Source Toolchains. This was hard for an FPGA newbie like myself to figure out. I was able to get a Blinky example to finally work after a sharp learning curve. Now, the good news is, I am now prepared to start experimenting with toolchains that support the dev board  from the same company as the FPGA chip.image


I will  be evaluating the use and helpfulness of customer support on the Lattice MachX03LF FPGA chip, MachX03LF Starter kit itself and the Software Development Toolchains available. I will also be discovering and evaluating the available User Forums and Knowledge Base available on the Lattice Site, that hopefully will aid me in my experiments. I will also be using the Resources (Documentation, Video's, Tutorials ) available on the Lattice Website. I will be including links throughout my review and in the "references" section at the end of this review.



UnBoxing of the Dev Board

First off, to clear up any confusion as of delivery date ( 08/28/2021) the roadtest page Summer of FPGAs -- Lattice MACHXO3LF Starter Kit

page contains the wrong part number for the kit.

  • The name of the product is:    "MachXO3LF Starter Kit" part# is "LCMXO3LF-6900C-S-EVN".
  • The Lattice FPGA part# is:      "LCMXO3LF-6900C-5BG256C"
  • Looks like references to the part#  on this page dropped the "F".
  • The LCMXO3LF-6900C-5BG256C is Flash Based
  • The Lattice  box sticker follows for clarification:


Unboxing Photos

I received the Kit from Newark with the Lattice box packed inside a nicely packaged box.

The board was packaged in plastic  with a USB Mini B Cable.



The packaging was a little difficult to allow removal of the board. I'm accustomed to a box that contains the board in a electrostatic bag. instead the board was suspended in plastic, secured down with two dimples as described in the photo's below


Managed to get the board out of plastic and took this Photo


The following instructions are shown in these two photo'sThe "getting started" instructions up close.
Front view of the boardBack view of the board
The FPGA chip up close








Follow the " Getting Started" Instructions on the Package

The package instructions for using your MarchXO3F starter kit, are slightly different then the sequence of instructions for the user guide. I had already installed Diamond IDE for the OrangeCrab review and I had already started on the tutorial. But I used  the LCMXO3L-6900C-5BG256C, so I decided to follow these instructions along with plugging the board in for the first time.


I first visited the Lattice Website Page:

here are the steps I followed from the package instructions on the packaging shown in the photo above.


1. install latest version of Programmer

Downlead and Install Programmer

    • On the Lattice Software page:

     CLICK ON the following link to download Programmer



2. connect USB cable

  • I'm so glad they provide a cable. I don't have and USB mini-B cable lying around
    • Connect the cable to a PC and the boards USB connector.
    • As described, the  Blue LED illuminates and the and RED LED array slides from left to right
  • I have a lot of USB drivers installed on my PC as a result of other MCU evaluation, but I was interested to know, which ones were related to this board. I took a screenshot of the Device Manger's  Universal Seral Bus Controllers section Before and After the cable was attached and 3 NEW drivers are located under "Universal Serial bus controllers"
      • BEFORE ConnectionAfter Connection


  • II installed all 3 drivers in the first step. I'm not certain which controller is a associated to which driver I installed?
  • Once I had the connection made to the board and the demo running, I opened the MachXO3 Starter Kit User Guide
  • And attempted exercise the sections that I had read about before getting the board.

1. Run the Demonstration Design

    • Go to page 5 and review the Run the Demonstration Design section and try the different DIP Switch Setting and observe the LED Behavior in table 1.

2. Download Demo Designs

    • Then go to the  "Download Demo Designs" section on page 6 and run it on the IDE as directed, since the FTDI Chip USB hardware drivers should have already been installed as part of the Lattice Diamond installation:

3. Programming a Demo Design with the Lattice Diamond Programmer

    • Then try  "Programming a Demo Design with the Lattice Diamond Programmer" on page 7 of the user guide. to see how the toolchain works.
    • I tried this and it appears that these are the instruction for use with the LCMXO3L-6900C-5BG256C (NVCM Based) board
    • The user guide mentioned on page 2,  that there are  two possible MachXO3 FPGA chips: LCMXO3L-6900C-5BG256C (NVCM Based) or LCMXO3LF-6900C-5BG256C (Flash Based) SO the same user guide can be used for both.

    • But I'm finding that there is a big difference in how you deploy the code to the FPGA thru the Programmer Utility.
    • Because when I used a .jed file and set the properties, this worked. Refer to the dialog setting below.
    • The problem is described below.
      • image
    •            LCMXO3LF-6900C-5BG256C (Flash Based)  Setting that worked
      •           I used a .JED file and set the device properties as follows



3. check out for the user guide and Examples

  • I'll make a NOTE here to revisit the examples and experiment with them


4. Download the Diamond software

  • I had already installed Diamond IDE for the OrangeCrab review and I had already started on the tutorial.
  • But I used  the LCMXO3L-6900C-5BG256C
  • So i used this version of the IDE


Prior to Getting My Board

Review the User Guide

  • Prior to getting the Machox03LF, I did some research on the board using the user guide provided on the Roadtest Page. I made some comments below on my findings.


  • Start by opening the MachXO3 Starter Kit User Guide
    • This guide describes how to start using the Starter Kit.
    • It describes the features of the board ( included here for reference)


  • — MachXO3 FPGA – LCMXO3L-6900C-5BG256C (NVCM Based) or LCMXO3LF-6900C-5BG256C (Flash Based)
    • Note: the kit contains the FPGA chip LCMXO3LF-6900C-5BG256C (Flash Based)

  • — USB mini-B connector for power and programming
  • — 4-Mb Serial Flash Memory for boot image and dual-boot support.
  • — Eight LEDs — 4-position DIP switch
  • — Momentary push button switch
  • — 40-hole prototype area
  • — Four 2 x 20 expansion header landings for general I/O, JTAG, and external power
  • — 1 x 8 expansion header landing for JTAG
  • — 1 x 6 expansion header landing for SPI/I2 C
  • — 3.3 V and 1.2 V supply rails
  • Pre-loaded Demo
    • – The kit includes a pre-loaded counter design that highlights use of the embedded MachXO3 oscillator and programmable I/Os configured for LED drive.
  • USB Connector Cable
    • – The board is powered from the USB mini-B socket when connected to a host PC. The USB channel also provides a programming interface to the MachXO3 JTAG port.
  • • Lattice Development Kits and Boards Web Page
    • – Visit for the latest documentation (including this guide) and drivers for the kit.
    • Note: The above link is brokenimage

  • • The content of this user’s guide includes
    • demo operation
    • programming instructions
    • top-level functional descriptions of the Starter Kit
    • descriptions of the on-board connectors
    • and a complete set of schematics


DO NOT PLUG IN THE USB CABLE and give power to the board yet...

The instructions are out of order in IMHO.

The Guide states on page 5 after it tells you to run the demo program?

"WARNING: Do not connect the board to your PC before you follow the driver installation procedure of this section.

Communication between the board and a PC via the USB connection cable requires installation of the FTDI chip

USB hardware drivers. Loading these drivers enables the computer to recognize and program the board. Drivers

can be loaded as part of the installation of Lattice Diamond design software or Diamond Programmer, or as a

stand-alone package."


  • Since I did not have my board yet I reviewed pages 5 thru 7 but did not exercise the instructions given on the Demonstration Design. but I planned to follow these instructions once I received the board. Which I did as I described above in the get started section.


Created an account on the the Lattice Website

  • Before you do anything else at this point you should Create an account on the Lattice Website.
    • See Appendix A below for instructions on registering a new account on
      • You will need an account to downlead the Toolchains and some documentation you might need.

Installed the Diamond IDE

  • Now you need to get the Diamond IDE software and installation document from the Diamond IDE Page . I narrated the process in Appendix B below.

Reviewed Diamond Training Videos and Documents

Lattice Toolchains

Diamond IDEimage

    • Install Lattice Diamond IDE on Windows10 and/or Ubuntu if you have not already.
    • Utilize the Lattice Customer support Portal if you run into trouble.
    • Experiments

Experiment# 1 -- Learning Diamond IDE using the Tutorial Document

      • I went through this tutorial before I received the board.
        • I was able to get thru Task 1 thru 13 without the MachX03LF.
        • instead of specifying MachXO3LF
          • Target Device: LCMXO3L-6900C-5BG256C Device Family: MachXO3L

          • Device Type: LCMXO3L-6900C Package Type: CABGA256

      • This is a very excellent tool to learn the workings of FPGA's and
      • I did get an error trying to run the simulation in TASK 3, but other that that I was really impressed with the content .
      • I learnt a great deal about the Software Flow in the product and I now have acquired the knowledge that I need o use the tool.
      • I logged a ticket on the error I was receiving during Simulation
        • I share the results in Appendix D
      • I stopped at TASK 13 "Download a Bitstream to an FPGA", since I hadn't received my board yet.
      • But then when I received the board I needed to redo the tutorial using the device family LCMXO3LF
      • I found this out by using the generated bit file and tried to run programmer and use the bit map generated with MachXO3L but it said it was incompatible
      • So I figured out a way to change the Target device as follows and rebuild the code as follows:
        • In the IDE double click on the device name and device selector dialog shows, change to Mach03LF LCM03LF-6900C
        • You need to rebuild the PLL with IPExpress
        • ReRun all stages and generate a .JED file
        • review and follow Task 13: Download a Bitstream to an FPGA section
        • use the settings for LCM03LF as above
        • Program runs but All LED's are solid?
        • Is it Working?
      • Finish running thru the following sections
        • Task 13: Download a Bitstream to an FPGA
        • Task 14: Add On-Chip Debug Logic
        • Task 15: Perform Logic Analysis
        • not sure what they did but it was interesting.


What I've gained from this tutorial

      • I learned that the programmer is different for the Mach03LF a Flash based option as opposed to the MachXO3L a NVCM Based option.
      • The following flow really helped me understand the complicated toolchains of the IDE. I pulled it directly out of the tutorial document, because it depicts the who process. I'll be refering to this as I learn more about the toolchain.
      • image
        • The solid arrows point to the major execution flow of the basic strategy used to build and embed the HDL to the board.
        • The dotted arrows point to task that can be used during development and analysis of the program logic of your design.
        • You should generate a .jed file instead of a .bit file.
        • Here are the strategy process tree showing the solid arrows depicted in the flow diagram above
        • image


Experiment# 2 - SEU (Single Event Upset) demo for the Mach03LF Starter Kit

      • This section describes my second experiment with the Mach03LF kit.
      • The pdf document introduces the example as:
        • "This document provides technical information and instructions for using the Single Event Upset (SEU) demo design from Lattice Semiconductor. This demo demonstrates the functionality of Soft Error Detection (SED) and Soft Error Correction (SEC) using the MachXO3LF starter kit. This document provides a description of the demo design as well as instructions for running the demo. The demo design makes use of Lattice Diamond® software feature of Soft Error Injection (SEI) to induce an SRAM bitflip error. This error is then detected by the FPGA SED feature running on the board. Finally, the demonstration shows the MachXO3LF device’s ability to correct the inserted error (SEC feature) without interruption of the user function."
      • What I did, was to download the following 2 resources from the "Documentation" section on the Page.
      • image
      • User Manual section - the following PDF file
      • Design File section - the following Zip file
      • I unzipped the demo to my local drive and opened the PDF file.
      • I followed the instructions in the document and  took these videos of my results, since the document did not include any result videos
      • At the end of section 8.1

        showing the rotating LEDs from D9 to D3

        At the end of section 8.2

        Showing the LEDs  D9 to D3 rotating and LED D2 remaining on indicating the SEI error

        At the end of section 8.3

        Showing that the LED D2 will extinguish, confirming Soft Error Correct (SEC)


Experiment Summary & Conclusions

      • This demo introduced me to the Lattice Programmer device setting for both .jed and
      • I learned more about the use of the stand-alone Lattice Programmer
      • the demo design consist of two major parts:
        • SED Module -- Which performs read and error detection of SRAM content
        • User logic - includes soft error indication and a function block that rotates the LEDs on board.
      • I was able to analyze the code to see how things were working.
      • I managed to run the demo with no problems,
      • The demo document is informative and very well put together.


Experiment# 3 - Hitless Update Demo

      • This section describes my Third experiment and documents
        1. How to get the instructions and code to run the example.
        2. What I Learned from working through this demo
      • The pdf document introduces the example as:
        • "In mission critical systems such as data center, storage or networking equipment, feature improvements and bug fixes are performed through background updates. However, up to now, designers have been avoiding updating of the control Programmable Logic Device (which typically performs functions such as power management, reset management, glue logic and other housekeeping functions on the board) as it forced a power cycle or reset of the entire system to enable the new algorithm to take effect.

The Lattice Semiconductor MachXO3TM device, the most popular control PLD, can be updated in the background and the new algorithm takes effect without interrupting board-level operations. There is no need for a power-cycle or reset of the device or the system. This feature is known as the hitless or zero-downtime system update."

      • To run the demo, download the following 2 resources (Instructions and Files) from the "Documentation" section on the Page.
        • Be aware that the Documentation Table has two Tabs that you have to navigate to 1." User Manuals" and 2. "Design Files" to get the instructions and code files for the demo. As describe in the picture below.
        • image

Experiment Summary & Conclusions


      • To conduct my experiment, I followed the documentation. This was very helpful in understanding how the "Hitless" feature.
      • This user guide introduced me to the following concepts and features:
        • Documented the Hitless Design
          • Theory of operation
          • User design block
          • Multiplexer Latch to hold outputs
          • Message Control Blocks
        • Running the code.
          • The steps to exercise the hitless feature
          • Each step was explained.
          • he Lattice Diamond® Programmer software is used to enable key features such as TransFR and Leave Alone.
        • Rebuilding the Design
          • A brief description on how to load the demo project file into Lattice Diamond IDE
          • I was introduced to the concept of two implementations in the project and how to set the appropriate implementation to active.
          • Run the Synthesize Design  stage and view the spreadsheet View  to assure that the ENABLE_TRANSFER Global Preference is Enabled
          • Run the entire Process to generate the bitstream file.



      • The experiment ran fairly smoothly without any major problems.
      • I did learn a little about the kit and programming it from working through the demo.
      • I did find two minor problems with the steps in the user guide though that I'd like to mention. In no way did this stop me from executing the demo.
        1. You need to be aware of the following described documented SW2 setting will running the steps in the demo. It was confusing to me on when these setting should be toggled?

Toggle switch (SW2 position 1) to differentiate between the power

on and hitless update operation.

Down (0) – Power on

Up (1) – Hitless Update


2. In section 8, I could not run the Programmer within Lattice IDE as I have for my other experiments?

          • The .XCF file is crossed out for both implementations and the programmer widget reports an error trying to find the file?
          • I was able to exit out of the IDE and Run the Stand alone Programmer as described in Section 7 "Running the Demo".
            • image



Lattice Propel Design Environment

    • Propel combines two powerful tools, Lattice Propel Builder (for IP system integration) and Lattice Propel SDK (for application software development). Propel makes it easy for developers of any skill level, from a novice FPGA developer to a seasoned pro, to quickly design Lattice FPGA-based applications.image
    • For example, novice users unfamiliar with how to write RTL code can still create designs using Lattice FPGAs thanks to Propel’s easy-to-use GUI. They simply drag-and-drop the required IP blocks into their design, and Propel automatically updates the design layout to incorporate the new IP. Alternatively, an experienced FPGA developer can quickly optimize their applications or port them to another Lattice FPGA by making direct edits to the FPGA’s code using Propel Builder’s script-level editing tool.
    • Propel also makes it easy to implement processor-based applications thanks to support for eight different processor core and peripheral IP blocks at launch, with more to come in the future. Particularly significant is Propel’s support for a RISC-V IP core; Lattice is the first Flash and SRAM-based FPGA supplier to do so. As RISC-V is open source, the processor architecture is increasingly popular with hardware developers as it keeps them from being locked into using proprietary processing IP.
    • Propel also lets software developers start developing before the hardware design is complete, another big development time saver. The Lattice Propel SDK makes this possible by providing industry-standard software development tools and libraries so developers can quickly and easily build, compile, analyze, and debug their application software.
    • It isn't clear at this writing, if Propel is supported on the MachX03LF Starter Kit? But I started researching it and attended a free Webinar that can be attended by visiting the Summer of FPGA:  Building Processor Based Systems on Lattice FPGAs Using Propel  page.  My interest is to experiment with the available RISC-V IP core as the SoC and to implement a simple Hello World program on the processor. I'm excited to work through the Propel tool Manuals to learn more. The RTL created by Propel Builder is imported into Diamond IDE for processing and sent to the board with Programmer.
    • Here is a block diagram of the 3 Lattice Toolchains
      • Propel Builder
        • Using Local and Server IP, the Propel Builder is used for SoC design, then to export the RTL to the Diamond IDE. And the CPU description, memory map and Drivers to the Propel SDK tools for software development.
      • Propel SDK
        • Once proceed by the SDK tools, the executable code is sent to the RTL in Diamond to allow it to run on the SoC design.
      • Diamond IDE
        • Then the RTL is processed and analyzed by running thru the Synthesis, Place & Route Design, and Programmer to create the Bitstream to the MachX03LF
        • Debugging can be implemented with a JTAG Server into the Reveal Debugger.


Install Lattice Propel

    • If you already have Diamond IDE installed and Licensed, you will still need to Get a license and install it to the license directory pointed to by Environment Variable LM_LICENSE_FILE. This will not affect the use of Diamond. You will still be able to run all 3 tools with the Propel License.
    • Install the software using the manual downloaded from the "Software Downloads & Documentation" section of the Propel page
    • image
    • Or click this button Lattice Propel 2.0 Installation for Windows User Guide


Lattice Propel Builderimage

    • An easy to use system IP integration environment, Propel Builder provides tools to integrate processors and peripheral IP. The graphical integration environment features an easy-to-use, drag and drop correct-by-construction methodology. All commands are Tcl scriptable.
    • Get the Builder user guide from the  "Software Downloads & Documentation" section of the Propel page.
    • image
    • Or click this button Lattice Propel Builder 2.0 User Guide

Lattice Propel SDKimage

    • A seamless software development environment, Propel SDK is a software development kit (SDK) with an integrated industry standard IDE and toolchain. The SDK features SW/HW debugging capabilities along with software libraries and board support packages (BSP) for Propel Builder defined systems.

Summary & Conclusions

    • I plan to go thru the entire 2 user guides to experiment with the available RISC-V IP core as the SoC and to implement a simple Hello World program on the processor.
    • There’s a lot to learn about Lattice Propel, including learning more about the design environment’s features, capabilities and a step-by-step development of a working system using the design environment.
    • This will be an ongoing effort even after this review is submitted.
    • This a very complex tool and my Electrical Design experience is probably making it more difficult then it really is.
    • I'm also not seeing any solutions for the MarchX03LF kit on the Propel Web page yet. I will be keeping an eye out for thee to experiment with.


Lattice Customer Support Resources


Support Portal



    • Technical Support Request

    • image


Knowledge Base


Summary & Conclusions

Some Questions?

  • I posed some question to myself while learning about FPGA Toolchains. Some are answered and some are still unanswered.
    • Can you place this board on a Breadboard?
      • ANS: seems so with headers. I'd be interested in what you folks feel. My soldering skills are minimal!
      • If so, Some projects ?
    • How easy is it to implement a simple Blinky Experiment?
      • ANS: YES .... I came to answer this myself
    • Can you run toolchains on windows 10?
      • ANS: YES
        • Lattice Diamond will install on Windows10
        • All experiments were run on Toolchains running on windows.
    • ____________________


  • I was able to get the Lattice Middleware up and running fairly quickly thanks to the fine documented demo and Lattice Toolchain docs and Video's.
  • After a little confusion on the Part# that I was actually using the Experiments I conducted with Lattice Diamond IDE real well.
  • I was using the installation that I had installed for my previous review on the OrangeCrab, but never used it until this review.
  • I installed and experimented with the Propel tool to experiment with designs using the RISC-V soft Processor.
  • I used the Customer support Portal to get answers to problems I was having when I was stuck and received my answers.
  • I reviewed and watch all the Documents and Video's available for the Tool Chains and Demos. These were a tremendous help in evaluatinting development on the kit.
  • I have just scratched the surface with my experimentations using this board and will continue using it to experiment with software development on an FPGA.
  • I have included a wish list of "Possible Future Experiments" that I am interested in trying out below.


  • This review was a challenge for me. I have a limited knowledge of  FPGA software development knowledge, but I do have a degree in computer science, did some Assembler, and have been a programmer for many years.
  • I was lucky to have participated in another FPGA Roadtest  Summer of FPGAs -- OrangeCrab Dev Bd - Review, which contained the Lattice ECP5 FPGA chip.
    • I was unable to experiment with the Lattice toolchains though because the Lattice Programmer would not connect to the OrangeCrab.
    • This review however really allowed me to Exercise the Lattice Toolchains quit extensively.
    • I plan on looping back to the OrangeCrab in the future and try to Implement Lattice Diamond IDE Development again.
  • The MarchX03LF is priced right and is an excellent entry level tool for experimenting with the technology for low budget makers, like myself.
  • I would like to touch upon my reasons for scoring like I did. I gave this kit almost a perfect score, which I have not done in the past. I enjoyed working with it so much that I could not score it any lower. What a great starter kit this is!!
  • Scoring Revisited

    • Product Performed to Expectations: 9

    • I gave this a 9, This is the way I envisioned using a starter kit to design and develop imbedded software. It was sort of what I thought developing with the Orange crab would be, but that didn't turn out to be the case.
    • Specifications were sufficient to design with: 9

    • I gave this a 9, For a novice to FPGA ,the design specification looked top-notch. The Demo specs were very well written.
    • Demo Software was of good quality: 9

    • I gave this a 9, Other than a few minor glitches and confusion on my part, the Code was very well written and more importantly worked as specified.
    • Product was easy to use: 10

    • I gave this an 10,  Because this was so easy to use that I was able to get running on the kit in no time. This allowed me to get results from my experiments and not have to figure out why thinks were not working.
    • Support materials were available: 10

      • I gave this a 5, because I can't say enough about the materials available to use with programming and design on the kit. The materials are extremely well done and concise. They were easy to understand for an FPGA novice like myself. I used them as a learning tool for teaching myself FPGA programming. They were so useful and will continue to be useful to me in my future experiments and Projects.
    • The price to performance ratio was good: 10

    • I gave this a 10, I'm a retired hobbyist and I'm on a budget.  Great price for what you get in hardware and Free toolchains. By far the best FPGA starter kit I have had the pleasure to evaluate.


Possible Future Experiments



Appendix A -- Instructions to Create a Lattice Website Account

  1. browse to
  2. Select "Register" on the right hand side of the Page header bar. If you already hace an account you obviously can "Sign In"
    1. image
  3. This will bring Up the "Register" page.
    1. image
  4. Complete the form as instructed and press the "create account" button and follow the instructions from here to complete your registration.


Appendix B -- Getting the Diamond IDE Software and Documents

  • Now that you've created your account, login to the site and go to the Diamond IDE landing page.
    • image
    • This is a very busy page, but it has everything you need to use the Diamond IDE.
    • You will need to scroll around to get to where you need to be but downloads, documents, licensing information, and videos are all here.
      • There is a "Jump To" bar a little ways down the Page (I found this navigation awkward),  especially the "Software Downloads & Documentation" section. More on this later....
        • image
    • Scroll a little ways up to the "Getting Started" section
      • image
    • These links will lead you the various sections on the page but follow them step by step
    • step 1 is straight forward.
    • step 2 is awkward because the link mention in this step throws you down to the "Software Downloads & Documentation" Section, but to get the installation document you need to:
      • select "Installation Guides"
        • image
      • then select the document from the list.
        • image
      • This is how to get all software and docs. This kind of threw me for a moment, but once you get the hang of it,  it's a breeze.
    • For  Step 3, I selected the FREE "Request Node-Locked License" and followed the instructions on the page to obtain a license .
      • You might choose a different license depending on your needs. The "node Locked License" is working great for my needs.
      • image
      • image


  • Now open the Installation doc you obtained in Step 3 and follow the installation instructions ( for windows mine was on page 10)
  • Now open the Dimond IDE to assure that is installed correctly.
  • And remember, If you get the Dialog box I'm showing in appendix C, Your license file has not been installed correctly. Review the installation  document and determine what you missed.


Appendix C -- Lattice Diamond IDE  ERROR!


You will need a free license file otherwise you receive this error when trying to run the Diamond IDE.


To get a license file follow the install guide for windows by downloading the install guide at  Lattice Diamond 3.12 installation guide for Windows .



Appendix D -- Error generated -- Trying to run Simulation example in Tutorial.

Lattice Support Portal Case ID



Error that was Generated

Received this error

Running Simulation example in Tutorial.

in document Lattice Diamond 3.12 Tutorial November 23, 2020

in section Task 3: Verify Functionality with Simulation



Error generated in ModelSim Transcript Box and the Wave screen is empty 





Sending file:sim_test3.mdo




Error generated in ModelSim Transcript Box and the Wave screen is empty  -----------------------------------------

# Reading pref.tcl

# do {G:/000 elem14 roadtest -5 - Lattice FPGA MachX03 L/MachXO3StarterKitDemo/MachXO3L_Starter_Kit/project/sim_test3/sim_test3.mdo}

# Loading project sim_test3

# Model Technology ModelSim - Lattice FPGA Edition vcom 2020.3 Compiler 2020.10 Oct 14 2020

# Start time: 11:27:09 on Aug 25,2021

# vcom -reportprogress 300 -work work G:/000 elem14 roadtest -5 - Lattice FPGA MachX03 L/MachXO3StarterKitDemo/MachXO3L_Starter_Kit/project/sim_test3/typepackage.vhd

# -- Loading package STANDARD

# -- Loading package TEXTIO

# -- Loading package std_logic_1164

# -- Loading package NUMERIC_STD

# -- Compiling package typepackage

# -- Compiling package body typepackage

# -- Loading package typepackage

# End time: 11:27:09 on Aug 25,2021, Elapsed time: 0:00:00

# Errors: 0, Warnings: 0

# Model Technology ModelSim - Lattice FPGA Edition vlog 2020.3 Compiler 2020.10 Oct 14 2020

# ** Error (suppressible): (vlog-1902) Option "-5" is not a valid option for this tool.

# Use the -help option for complete vlog usage.

# Errors: 1, Warnings: 0

# ** Error: C:/lscc/diamond/3.12/modeltech/win32loem/vlog failed.

# Error in macro G:\000 elem14 roadtest -5 - Lattice FPGA MachX03 L\MachXO3StarterKitDemo\MachXO3L_Starter_Kit\project\sim_test3\sim_test3.mdo line 21

# C:/lscc/diamond/3.12/modeltech/win32loem/vlog failed.

#     while executing

# "vlog  +incdir+G:/000 elem14 roadtest -5 - Lattice FPGA MachX03 L/MachXO3StarterKitDemo/MachXO3L_Starter_Kit/project/sim_test3  -work work  "G:/000 ele..."

#     invoked from within

# "if {![file exists "G:/000 elem14 roadtest -5 - Lattice FPGA MachX03 L/MachXO3StarterKitDemo/MachXO3L_Starter_Kit/project/sim_test3/sim_test3.mpf"]} { ..."






The MachX03LF Starter Kit

  • User Guide
    • A great place to start with Lattice Diamond IDE and using the pre-programmed blinky demo.
  • MachXO3LF Starter Kit
    • The official Lattice Website page for the kit
    • Contains a user guide (same user guide mentioned above) and example guides and designs specifically for the MachO3LF.

SEU Demo for MachXO3LF Starter Kit

MachXO3 Family Data Sheet

MachXO3 SED Usage Guide

MachXO3 Programming and Configuration Usage Guide

Training Video's

Available Videos ( taken from the bottom of the Diamond IDE Page )


Video Title



Diamond Overview

14:4828MBLattice Diamond software includes many new features. This video overview briefly covers several new features and abilities such as the new user interface, design flow, and several tool views that are available.

Diamond Installation Overview

4:0017MBPreview of step by step installation process of Lattice Diamond software

Diamond Licensing Overview

7:3130MBInstructional video on obtaining license and installation

Diamond Key Concepts

10:2521MBLattice Diamond software includes several new key concepts. This video discusses the structure of Diamond projects and the use of implementations, strategies, and folders within projects. Additionally the video discusses shared design memory use, and context sensitive views.

Diamond Importing from ispLEVER

4:4710MBLattice Diamond software uses a different project structure than the previous ispLEVER software. This video describes how to import an ispLEVER project into Diamond.

Diamond Design Flow Changes

8:2316MBLattice Diamond software features a similar design flow to previous software with some changes and enhancements. This video describes the design process flow and the use of the Process view, File List view, and Run Manager view.

Diamond Timing Analysis Overview

9:3621MBLattice Diamond software includes a new Timing Analyzer View that provides a rich graphical interface to viewing timing constraint paths, reports, and schematics. Additionally, the ability to change timing constraints and directly run a timing analysis without re-implementing the design significantly speeds the timing closure process. This video describes the management of the Timing Analyzer files, the new Timing Analyzer UI, and how to make timing constraint changes and generate new timing results.

Diamond Power Calculator

5:0613MBLattice Diamond software includes an improved Power Calculator view. A new feature is the ability to manage power project files (PCF) directly in the File List view. This video describes the management of the Power Calculator files and the behavior of the Power Calculator view.

Diamond Reveal Hardware Debugger

8:0914MBLattice Diamond software includes improved Reveal Inserter and Reveal Analyzer views for hardware debugging. The Reveal Analyzer view features a streamlined interface including an updated waveform display featuring multiple cursors and rubber banding for measurements. This video describes the management of the Reveal debug files and the new Reveal Analyzer waveform changes.

Diamond Simulation Flow

6:3711MBLattice Diamond software includes changes to projects that support multi-file simulation testbenches and allow different models for simulation or synthesis for a single module. The Simulation Wizard has been enhanced to parse for the simulation top and to pass this information and other options directly to a simulator. This video describes the simulation features provided with the software and their basic usage.

Diamond Tcl Scripting Support

2:415MBLattice Diamond software includes new Tcl dictionaries that provide the ability to script the design flow and several key views. This video describes the available Tcl dictionaries and how to run Tcl commands from the UI or the Tcl console.

Diamond Programmer

4:176MBLattice Diamond software includes Programmer that provides the ability to directly program one or multiple FPGA devices on the same scan chain. This video describes how to use it from the UI or outside of DIamond.

Lattice Website.

  • imagewell, a bribe would be good, but I think Randall has the addresses to the selection committee. I could use that bottle while working with FPGA's. as we say in Massachusetts, "it's wicked hard". It's like designing and building your own car before you can drive!


    My background is in Software and for me, designing electric circuits for MCUs is difficult enough, never mind designing an MCU. I have no assumptions about anything with electrical design and learning electronics on my own is what I've been doing over the past few years. I am a retired Software Engineer and always been interested in embedded programming. A good direction is very important to me and well written resource materials is very crucial to my learning path.

    It looks to me like the Microchip FPGA has that and I do plan on following the same outline as I did for the other 2 FPGAs If I am fortunate to be selected.


    There is also a Summer Of FPGAs - Design Challenge   that looks interesting.


    Thanks again for all your encouragement

    Steve K

  • AJ at the beginning of the summer FPGA program, I posted a comment about the FPGA water are fine just jump in. I decided to sit on the dock and not take the plunge. I'm still overwhelmed when I attend presentations on the topic. I have read some of SK's  reviews and see similarities in our approach to testing. I don't consider myself a bad swimmer but the FPGA waters are deep and finding a place to wade in is not widely available. Jumping in with the thought I could just swim didn't seem realistic for me. Based on the knowledge I am accumulating from the people participating, my decision to just watch from the dock and not swim was best for me.


    SK has gained some great knowledge and experience in the two FPGA review he has done. I figured leveraging that for another FPGA review was a no-brainer. There are some Uber technical folks in the E14 community that have be accused of getting more of the nicer product reviews. I won't mention names but I will say this, if their past reviews quality are any indication of future performance, awarding their application the RoadTest review made good business sense for the E14 RoadTest review committee.


    I am not, nor do I consider myself one of the Uber technical folks but I hold no grudge to those that are. They earned it in my opinion.

  • Sean, I've been playing around with the Ultra96-V2 and I have to say I'm finding the learning curve hard but very interesting: it's my first go with a FPGA.  It's hard enough that I wouldn't want to do a road test from anything but a beginner perspective to show "how I got on" because process is methodical, advancing but slow.  That seems a little unfair to the manufacturers though unless they specifically target at beginners.  So I'm sort of with you.  It's not been helped by fighting with Ubuntu (not the dev tools, just the £$%^@@ OS.)  I now have a Vidor 4000 courtesy of E14 so it will be interesting to have a go with that as a comparison to the Ultra96-V2.

  • Send me the addresses for the selection committee and I will send along a bribe? What does Randall drink ? I have a forty year old bottle of Scotch I can ship him. Customs might open it and drink a bit but that should concern him.  I'm thinking that selecting your application for that RoadTest would be of benefit from a shared knowledge perspective. Maybe part of your application pitch is a town hall gathering of all three RoadTests products providing your like and dislikes.


    I really did enjoy the FPGA newbie approach you took in this review. I consider myself a technical person but many times I'm a newb with technology.

  • Hi

    Nice to hear from you again.

    Thanks for reading thru my review. I'm starting to get the hang of FPGA development. I put an application in for the Summer of FPGAs: Microchip Polarfire FPGA Eval Kit

    You should consider this one and do like I did and jump in with both feetimage

    I appreciate your support


    Steve K

  • Ideal application selection for this RoadTest Randall and the RoadTest review committee. Combining the knowledge from a similar product evaluation with this review enhanced the details.


    I was looking forward to this review SK after reading the OrangeCrab review. I contemplated pitching an application for the FPGA products but decided against doing it because I was intimidated by the knowledge curve. It appears the knowledge gained from the first review helped in this review.


    Rather high marks in scoring. I was especially surprised in the Support Material available scoring. You typically find material available but it is stale for the product or the documentation is short. Support documentation that is lacking in quantity and quality is always frustrating when the learning is new.


    Great review man. I'm glad to see the struggles from the PoE review haven't jaded youimage

  • I‘d love to take credit for Jon’s work but I think he’d notice image

  •      Thanks   for reading my review. Good to know about the License renewal and the Pinout defining.

  • Your Welcome

    It's a very nice FPGA kit for the price. Thanks for reading it. Steve K

  • A good look at the Lattice design tools. I'm sure it will help anyone else who is new to working with FPGAs.


    I've been using the basic HDL stuff on Windows 8.1, which isn't one of the supported operating systems, and it's been fine except for a couple of very minor quirks. I can't vouch for the various soft-processor tools, though, because I haven't used them.


    Generally, I like the integrated environment they've done. The one thing that threw me a little was defining the pinout. I'd been used to using the graphical tool in the old Xilinx WebPack, and was aware of something similar in the Altera tools, so I spent a few minutes trawling through the help and their website before I accepted that there wasn't going to be a helpful widget to use and I had to do it directly with the constraints file.


    A small thing to note is that the free licence runs out after a year, as I suddenly discovered earlier this year after a period of not using it for anything. Relicensing it wasn't a problem, but it's the sort of thing you may want to consider in a commercial context.