Cmod S7: Breadboardable Spartan-7 FPGA Module - Review

Table of contents

RoadTest: Cmod S7: Breadboardable Spartan-7 FPGA Module

Author: tcmichals

Creation date: 21 Apr 2020

Evaluation Type: Development Boards & Tools

Did you receive all parts the manufacturer stated would be included in the package?: True

What other parts do you consider comparable to this product?: MAX 10, Cyclone 10LP, and ECP5 From Lattice.

What were the biggest problems encountered?: Getting up to speed with all of the software. Vivado, HLS, and Vitis applications are complex.

Detailed Review:

Review overview

• What to do first?  Reviewed the installation instructions and documentation for the CMOD-S7
  • Install the software needed to program and develop software applications using the CMOD-S7-25,
• Tools
  • Vivado: GUI/Command line to generate final bit-stream for the Spartan-7
  • Vitis:  Eclipse base tool to generate firmware for the Micro-blaze/ARM micro-controllers.
• Projects to try out the board and tool set
  • Basic LED flasher.  (Hello world for hardware developers)
  • Verilog only
  • Generate bit stream and load into FPGA
  • Micro-controller project to control AXI Devices
    • Send commands over the serial port to control LEDs
    • Simple HTML GUI
  • AXI Stream interfaces
    • Goal use HW to offload packet detection

Getting started:

• Install Vivado software (IDE to program the CMOD 7 Board)
• Downloaded board files and installed (This is included in the above instructions)  Installed the latest version 2020.1
  • The host OS is Ubuntu 20.04 LTS
    • Had to follow do this "patch" to install
      • 20.04 LTS is not yet supported

• Would recommend reading over the reference material
  • On the reference page there is a link to the XDC files, goto github and download CMod-S7-25-Master.xdc   A XDC file is used during the bit stream generation to map names to external pins. This file has all of the pins defined and formatted to <UPDATE>  Will explain more of this in a step by step guide.
  • Basics on how to use Vivado
  • Review the schematic
    • Two user buttons
    • 4 User Green LED
    • 1 User RGB LED
    • 2 User Analog 0 to 3.3

Hello World == blink LEDs

1. "Hello World", is a software application that prints out "Hello world" on an output device, the goal is to demonstrate and learn the basic skills of the programming language , tools, and execute environment.  The same basic approach of building a software application can also be applied to an FPGA, instead of printing out to a device, an LED is used.
   • There are 6 LEDs, for the "Hello World", the "application" will blink each of the LED's one after another.
   • Start vivado  (This is not a step by step instructions but, a basic guide on some features and high level steps)
   • Create a project

• Select the CMOD S7 board.  During the installation process, board files were installed for the CMOD-S7, this makes it easier and less error prone to creating a project.

• After selecting next, the project is configured

• Add IP to the diagram using the +, one of the first IP is to create PLL (clocking) block.  I used the defaults for this project (100Mhz)

• Next is to create a Block Design,  Here I used standard verilog from a directory and moved the hello_world.v onto the diagram

• Vivado will assist at times to connect blocks together  Use the xdc (constraints file) and connect the LEDs on the board.  The xdc file is included in the documentation.

• One important step it to create an HDL wrapper, is it the top most level of the design. Now, generate the bit-stream.  This step takes your verilog code, compiles, does timing checks, fitting, then creates the file to load into the FPGA (bit-stream)

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• Once this completes without an error, can load into the FPGA and see your LEDs blink all within the GUI.

The next project was using a soft core processor (microblaze), there are two choices for software bare-metal or RTOS (FreeRTOS)

• Started a new project, used the board CMOD-S7 files, same as above.  Created a Block design and added PLL used 96Mhz for the clock.  This clock drives the entire design. Here is the block design
• This uses local memory, 64K.  This is divided into ROM (Your Code) and RAM.  The tools allow you to configure the sizes.  Used GPIO controllers for the LED controls.  Must have a UART and a Timer if FreeRTOS is used.  The tools will not generate a RTOS if either is missing.  Once the design is compiled into a bit-stream.  The hardware design is exported along with the bit-stream.  This will be used by Vitis to create the FreeRTOS BSP then you can create an application based on the BSP.

• I did a customization of FreeRTOS heap, the default size is 64K, trimmed it down to 10K.    This application uses the xuartns55 c functions wrapped by FreeRTOS primitives (Queue) to receive bytes and transmit bytes.  The baud rate is 6Mbits.  The processor is loaded to keep up with the stream.  The protocol uses standard byte escape characters to frame a packet.  Also, what is nice about Vitis, allows for source level debugging, and tracing .
• One big issue is the project is using C++.  The C++ constructors for global object initialization,  posted on the forum and waiting for reply.  Here is a screen shot of a basic HTML interface.
• 
• The CMOD-S7 uses a FTDI chip that allows serial to be bridge over USB the maximum baud-rate is 12Mbits.

Offloading serial packet framing:

• The next project, is to use more of the Xilinx included IP, AXI stream to DMA
  • The goal is to use AXI stream, the stream will support start and end of frame.  The serial protocol I'm using has an unique byte for the start of frame and end of frame.
• The first project is to create a simple UART AI stream, the verilog code is leverage from repo on github. The repo has example for a simple loop-back.  Here is the diagram:

• The LEDs are the upper 4 bits and the external connector is the lower 4 bits.  Maybe it would be better to use the LEDs on the lower 4 its so using the keys 1 thru 7 would show up on the LEDs. But the goal was to validate 12Mbits is working.
• The next stage is to create another block, but have a AXI stream interface. So, created a fpga_axis verilog file, with two streams RX/TX.  Also, added a FIFO on the RX side, so if DMA is busy or processor is slow, the FIFO will buffer.  This IP comes with vivado. But, there is a critical warning, TLAST is not defined, oh, that is needed to tell the DMA to end the transfer for RX.  Here is a screen shot.

This is the power of having an FPGA, the processor will get interrupted when a frame is received instead of interrupt for each byte.  Also, AXI Stream can be connected back to back each block adding a little more functionality.

There is a lot of competition for DIP type FPGA boards, here are a few:

Each of these boards have different mix of I/O and features, so, it is hard have a matrix of features/cost/benefits.

The CMOD S7 Spartan Module has serial and JTAG.  It would be nice to have the serial interface be flexible to be changed between serial and Synchronous mode for high speed streaming.