Project Details-
MYIR Board AM437x RTOS as Master device transmitting data to slave through EtherCAT Communication(Protocol).
Motor as Slave, will receive the data over drive to run motor.
So here basically we are using the acontis master code for application.
We just want to start motor ON/OFF, so what basically command shall I send over in the code?
In the main.c code where shall I send to run the motor?
I've read the code the command i'm not getting / Code details ?
In which buffer is the data transmitted to slave?
Please suggest the solution.
I'have pasted main.c code below-
/*-----------------------------------------------------------------------------
* main.c
* Copyright acontis technologies GmbH, Weingarten, Germany
* Description EtherCAT Master demo application
*---------------------------------------------------------------------------*/
#include <xdc/std.h>
#include <xdc/runtime/Error.h>
#include <xdc/runtime/System.h>
#include <ti/sysbios/BIOS.h>
#include <ti/sysbios/knl/Task.h>
#include <ti/sysbios/family/arm/a8/Mmu.h>
#include <ti/sysbios/timers/dmtimer/Timer.h>
#include <ti/sysbios/hal/Cache.h>
/* EcMaster version */
#include <EcVersion.h>
/* includes from demo */
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
/* EMAC Driver Header File. */
#include <ti/drv/emac/emac_drv.h>
#include <ti/drv/emac/src/v4/emac_drv_v4.h>
#include <ti/drv/emac/soc/emac_soc_v4.h>
#include <ti/board/board.h>
#include <ti/drv/gpio/GPIO.h>
#include <ti/drv/gpio/soc/GPIO_v1.h>
#include <ti/starterware/include/hw/hw_control_am43xx.h>
#include <ti/starterware/include/hw/am437x.h>
#include <ti/starterware/include/ethernet.h>
#include <ti/sysbios/timers/dmtimer/Timer.h>
/* UART Header files */
#include <ti/drv/uart/UART.h>
#include <ti/drv/uart/UART_stdio.h>
/* Clock source macros for enabling specified DMTIMER */
#define CM_PER_TIMER3_CLKCTRL (0x44DF8800 + 0x538) // PRCM_CM_PER_TIMER3_CLKCTRL
#define CM_DPLL_CLKSEL_TIMER3_CLK (0x44DF4200 + 0x8)
#define DMTIMER3 3
#define TIMER_ID DMTIMER3
void TimerEmptyISR();
/********************************************************************************/
/** \brief Puts string to the UART and replace "\n" to "\n\r"
*
* \return N/A
*/
static int UARTPutStringWithCR(char* pStr, int maxLength)
{
int symCount = 0;
char* pCurrent = pStr;
while (*pCurrent != 0)
{
Char curChar = *pCurrent;
if ( '\n' == curChar )
{
UART_putc('\n');
UART_putc('\r');
}
else
UART_putc(curChar);
symCount++;
pCurrent++;
}
return symCount;
}
/********************************************************************************/
/** \brief Puts string to the UART
*
* \return printed symbols count
*/
#define MAX_TRACE_MSGLEN 255
int UARTVprintf(const char *szFormat, va_list vaArgs)
{
char achMsg[MAX_TRACE_MSGLEN];
vsnprintf(achMsg, MAX_TRACE_MSGLEN, szFormat, vaArgs);
return UARTPutStringWithCR(achMsg, MAX_TRACE_MSGLEN);
}
/* Enable the below macro to have prints on the IO Console */
//#define IO_CONSOLE
#ifndef IO_CONSOLE
#define NIMU_log UART_printf
#else
#define NIMU_log printf
#endif
/* ========================================================================== */
/* Macros */
/* ========================================================================== */
#define MAX_TABLE_ENTRIES 3
#define GPIO_USER0_LED_PIN_NUM (0x0B)
#define GPIO_USER0_LED_PORT_NUM (0x05)
#define GPIO_USER1_LED_PIN_NUM (0x0A)
#define GPIO_USER1_LED_PORT_NUM (0x05)
#define SYS_MMU_BUFFERABLE 1
#define SYS_MMU_CACHEABLE 2
#define SYS_MMU_SHAREABLE 4
#define SYS_MMU_NO_EXECUTE 8
/* ========================================================================== */
/* Global Variables */
/* ========================================================================== */
/**Task handle for EIP*/
Task_Handle main_task;
uint8_t board_type = 0;
//NIMU_DEVICE_TABLE_ENTRY NIMUDeviceTable[MAX_TABLE_ENTRIES];
void TaskFxn(UArg a0, UArg a1);
/* GPIO Driver board specific pin configuration structure */
GPIO_PinConfig gpioPinConfigs[] = {
/* Input pin with interrupt enabled */
GPIO_DEVICE_CONFIG(( GPIO_USER0_LED_PORT_NUM + 1 ), GPIO_USER0_LED_PIN_NUM) |
GPIO_CFG_IN_INT_RISING | GPIO_CFG_INPUT,
/* Output pin */
GPIO_DEVICE_CONFIG( (GPIO_USER0_LED_PORT_NUM + 1), GPIO_USER0_LED_PIN_NUM) |
GPIO_CFG_OUTPUT
};
/* GPIO Driver call back functions */
GPIO_CallbackFxn gpioCallbackFunctions[] = {
NULL,
NULL
};
/* GPIO Driver configuration structure */
GPIO_v1_Config GPIO_v1_config = {
gpioPinConfigs,
gpioCallbackFunctions,
sizeof(gpioPinConfigs) / sizeof(GPIO_PinConfig),
sizeof(gpioCallbackFunctions) / sizeof(GPIO_CallbackFxn),
0,
};
/* ========================================================================== */
/* Local Variables */
/* ========================================================================== */
typedef struct _sys_mmu_entry
{
void* address;
/**< Address to be entered in MMU table. */
unsigned int attributes;
/**< Attributes of the memory. */
}SYS_MMU_ENTRY;
SYS_MMU_ENTRY applMmuEntries[] = {
{(void*)0x30000000,SYS_MMU_CACHEABLE}, //QSPI CS0 Maddr1space - Cacheable
{(void*)0x30100000,SYS_MMU_CACHEABLE}, //QSPI CS0 Maddr1space - Cacheable
{(void*)0x30200000,SYS_MMU_CACHEABLE}, //QSPI CS0 Maddr1space - Cacheable
{(void*)0x30300000,SYS_MMU_CACHEABLE}, //QSPI CS0 Maddr1space - Cacheable
{(void*)0x40300000,0}, //OCMCRAM - Cacheable
{(void*)0x44D00000, SYS_MMU_BUFFERABLE}, //PRCM - Non bufferable| Non Cacheable
{(void*)0x44E00000, SYS_MMU_BUFFERABLE}, //Clock Module, PRM, GPIO0, UART0, I2C0, - Non bufferable| Non Cacheable
{(void*)0x47900000,SYS_MMU_BUFFERABLE}, //QSPI MMR Maddr0space
{(void*)0x48000000, SYS_MMU_BUFFERABLE}, //UART1,UART2,I2C1,McSPI0,McASP0 CFG,McASP1 CFG,DMTIMER,GPIO1 -Non bufferable| Non Cacheable
{(void*)0x48100000,0}, //I2C2,McSPI1,UART3,UART4,UART5, GPIO2,GPIO3,MMC1 - Non bufferable| Non Cacheable
{(void*)0x48200000, SYS_MMU_BUFFERABLE}, //
{(void*)0x48300000, SYS_MMU_BUFFERABLE}, //PWM - Non bufferable| Non Cacheable
{(void*)0x49000000, SYS_MMU_BUFFERABLE}, //EDMA3CC - Non bufferable| Non Cacheable
{(void*)0x4A000000, SYS_MMU_BUFFERABLE}, //L4 FAST CFG- Non bufferable| Non Cacheable
{(void*)0x4A100000, SYS_MMU_BUFFERABLE}, //CPSW - Non bufferable| Non Cacheable
{(void*)0x54400000, SYS_MMU_BUFFERABLE}, //PRU-ICSS0/1 -Bufferable| Non Cacheable | Shareable
{(void*)0x80000000,SYS_MMU_CACHEABLE}, //QSPI CS0 Maddr1space - Non bufferable| Non Cacheable
{(void*)0xFFFFFFFF,0xFFFFFFFF}
};
int SDKMMUInit(SYS_MMU_ENTRY mmuEntries[])
{
unsigned short itr = 0;
Mmu_FirstLevelDescAttrs attrs;
if(NULL == mmuEntries)
return -1;
Mmu_disable();
Mmu_initDescAttrs(&attrs);
attrs.type = Mmu_FirstLevelDesc_SECTION;
attrs.domain = 0;
attrs.imp = 1;
attrs.accPerm = 3;
for(itr = 0 ; mmuEntries[itr].address != (void*)0xFFFFFFFF ; itr++)
{
attrs.bufferable = ((mmuEntries[itr].attributes) & SYS_MMU_BUFFERABLE) && 1;
attrs.cacheable = ((mmuEntries[itr].attributes) & SYS_MMU_CACHEABLE) && 1;
if (!attrs.bufferable && !attrs.cacheable)
attrs.tex = 0; //tex is initialized to 1 and need this to force strongly ordered
attrs.shareable = ((mmuEntries[itr].attributes) & SYS_MMU_SHAREABLE) && 1;
attrs.noexecute = ((mmuEntries[itr].attributes) & SYS_MMU_NO_EXECUTE) && 1;
Mmu_setFirstLevelDesc((Ptr)(mmuEntries[itr].address), (Ptr)(mmuEntries[itr].address) , &attrs); // PWM
}
Mmu_enable();
return 0;
}
void CpswPortMacModeSelect(uint32_t portNum, uint32_t macMode)
{
uint32_t regVal = 0U;
regVal = HW_RD_REG32(SOC_CONTROL_MODULE_REG + CTRL_GMII_SEL);
switch(macMode)
{
case ETHERNET_MAC_TYPE_MII:
case ETHERNET_MAC_TYPE_GMII:
if(1U == portNum)
{
HW_SET_FIELD(regVal, CTRL_GMII_SEL_GMII1, 0U);
HW_SET_FIELD(regVal, CTRL_GMII_SEL_RGMII1_IDMODE, 0U);
HW_SET_FIELD(regVal, CTRL_GMII_SEL_RMII1_IO_CLK_EN, 0U);
}
else if(2U == portNum)
{
HW_SET_FIELD(regVal, CTRL_GMII_SEL_GMII2, 0U);
HW_SET_FIELD(regVal, CTRL_GMII_SEL_RGMII2_IDMODE, 0U);
HW_SET_FIELD(regVal, CTRL_GMII_SEL_RMII2_IO_CLK_EN, 0U);
}
else
{
/* This error does not happen because of check done already */
}
break;
case ETHERNET_MAC_TYPE_RMII: /* RMII */
if(1U == portNum)
{
HW_SET_FIELD(regVal, CTRL_GMII_SEL_GMII1, 1U);
HW_SET_FIELD(regVal, CTRL_GMII_SEL_RGMII1_IDMODE, 0U);
HW_SET_FIELD(regVal, CTRL_GMII_SEL_RMII1_IO_CLK_EN, 0U);
}
else if(2U == portNum)
{
HW_SET_FIELD(regVal, CTRL_GMII_SEL_GMII2, 1U);
HW_SET_FIELD(regVal, CTRL_GMII_SEL_RGMII2_IDMODE, 0U);
HW_SET_FIELD(regVal, CTRL_GMII_SEL_RMII2_IO_CLK_EN, 0U);
}
else
{
/* This error does not happen because of check done already */
}
break;
case ETHERNET_MAC_TYPE_RGMII: /* RGMII */
if(1U == portNum)
{
HW_SET_FIELD(regVal, CTRL_GMII_SEL_GMII1, 2U);
HW_SET_FIELD(regVal, CTRL_GMII_SEL_RGMII1_IDMODE, 0U);
HW_SET_FIELD(regVal, CTRL_GMII_SEL_RMII1_IO_CLK_EN, 0U);
}
else if(2U == portNum)
{
HW_SET_FIELD(regVal, CTRL_GMII_SEL_GMII2, 2U);
HW_SET_FIELD(regVal, CTRL_GMII_SEL_RGMII2_IDMODE, 0U);
HW_SET_FIELD(regVal, CTRL_GMII_SEL_RMII2_IO_CLK_EN, 0U);
}
else
{
/* This error does not happen because of check done already */
}
break;
default:
break;
}
HW_WR_REG32((SOC_CONTROL_MODULE_REG + CTRL_GMII_SEL), regVal);
}
/**
* \name main
* \brief Main Function
* \param none
* \return none
*
*/
int main(void)
{
/* Call board init functions */
Error_Block eb;
Board_initCfg boardCfg;
Task_Params taskParams;
SDKMMUInit(applMmuEntries);
boardCfg = BOARD_INIT_PINMUX_CONFIG | BOARD_INIT_MODULE_CLOCK | BOARD_INIT_UART_STDIO;
Error_init(&eb);
Board_init(boardCfg);
/* Chip configuration MII/RMII selection */
CpswPortMacModeSelect(1, ETHERNET_MAC_TYPE_RGMII);
CpswPortMacModeSelect(2, ETHERNET_MAC_TYPE_RGMII);
Task_Params_init(&taskParams);
taskParams.priority = 1;
taskParams.stackSize = 0x1400;
taskParams.instance->name = "MainTask";
main_task = Task_create (TaskFxn, &taskParams, &eb);
BIOS_start();
return(0);
}
/** \brief Auxiliary clock timer instance.
*
* Used inside EcMaster code for auxiliary clock.
* If instance is NULL, than standard clock is used (not precise).
*/
Timer_Handle g_auxClocksTimerHandle = 0;
/*****************************************************************************/
/** \brief Initializes timer instance which is used from auxiliary clock.
*/
void InitAuxClockTimer()
{
Error_Block eb;
Timer_Params auxTimerParams;
// clock source to CLK_M_OSC: 0x1 - high frequency input clock
// CLK_32KHz: 0x2
// TCLKIN : 0x0 - external clock pin - not used.
*(unsigned int*)CM_DPLL_CLKSEL_TIMER3_CLK = 0x1;
/* enable the TIMER */
*(unsigned int*)CM_PER_TIMER3_CLKCTRL = 0x2;
Error_init(&eb);
Timer_Params_init(&auxTimerParams);
auxTimerParams.period = 2400; // default extFreq.lo=24000000
auxTimerParams.periodType = Timer_PeriodType_COUNTS;
auxTimerParams.arg = 1;
g_auxClocksTimerHandle = Timer_create(TIMER_ID, TimerEmptyISR,
&auxTimerParams, &eb);
if (g_auxClocksTimerHandle == NULL) {
System_abort("Aux Timer create failed");
}
}
/*****************************************************************************/
/** \brief Timer ISR which do nothing.
*/
void TimerEmptyISR()
{
}
/*****************************************************************************/
/** \brief Prototype of main task defined in another file.
*
*/
extern int EcMasterDemo(void);
/**
* \name TaskFxn
* \brief Task which do EIP initialization
* \param a0
* \param a1
* \return none
*
*/
void TaskFxn(UArg a0, UArg a1)
{
NIMU_log("\n\rSYS/BIOS EcMasterDemo CPSW Sample application\n\r");
InitAuxClockTimer();
/* Workarround call to cache function should exist in executable becuase linker does not want to add it */
Cache_wbInv(&main_task, 1, Cache_Type_ALL, TRUE);
EcMasterDemo();
}