Single Pair Ethernet Quiz

An interesting quiz. PoDL implementation for 10Base-T1S is a curious one.

yes - have you seen any reputable implementations? it seems not being standardized yet (or I didn't manage to find correct information)

No, I haven't.

The really odd thing is that the PoDL 802.3cg/bu standard is not designed for hot plug in / plug out. It appears to assume that once the system is set up, that's it, or if you want to insert a new PD device then you power the whole system down to do it. I suppose this thinking originates from the automotive industry where you'd see this in an automotive system.

Yesterday, I even asked Gemini AI to provide me with some insight on PoDL implementation in a 10Base-T1S, and this is the detailed response. Make of it as you see fit.

Google Gemini response:

Okay, let's look at how PoDL (Power over Data Lines) detection and power delivery work in a 10BASE-T1S daisy-chain configuration, as defined under IEEE 802.3cg.

The 10BASE-T1S standard is specifically designed for multi-drop segments, which can be implemented as a bus or a daisy chain, connecting multiple devices onto the same single pair. PoDL adds the complexity of delivering power over this shared pair.

Here's how it works, focusing on the detection and power aspects in a daisy chain (PSE -> PD1 -> PD2 -> ... -> PDn):

1. Detection Phase in a Daisy Chain:

• PSE Initiates: The PSE (at the start of the chain) initiates the detection sequence exactly as described before: applying Vdet_lo and Vdet_hi voltages.
• Signal Propagation: These DC detection voltages propagate down the chain, passing through each intermediate PD. The PDs are designed so that their input/output circuitry allows these low detection voltages to pass through relatively unimpeded, even when the PDs themselves are not fully powered.
• Combined Signature: The crucial difference is that the PSE doesn't just see the signature of the first PD (PD1). It sees the combined electrical signature of all valid PDs connected downstream. Each PD presents its detection V-I characteristic in parallel from the PSE's perspective.
• PSE Measurement: The PSE measures the total current drawn (or the resulting voltage drop) at its port in response to Vdet_lo and Vdet_hi. This measured response will reflect the sum of the currents drawn by PD1, PD2, ..., PDn's detection circuits.
• Validation: The PSE validates the measured response against the expected signature range for a valid PoDL segment. The standard accounts for the possibility of multiple PDs. The primary goal is to confirm:
  • At least one valid PD is present.
  • There isn't a fault condition like a short circuit (which would draw excessive current) or an open circuit beyond the first device (which might draw too little or no current, depending on PD1).
• Individual Detection? Standard PoDL detection typically confirms the presence of a valid segment rather than precisely identifying each individual PD device during this phase. It verifies the segment is properly terminated with PoDL-compliant devices.

2. SCCP Classification Phase in a Daisy Chain:

• Complexity: Classification via SCCP on a multi-drop or daisy-chain segment is more complex than point-to-point. All devices share the same communication medium.
• PSE Initiation: After successful detection, the PSE provides initial power and initiates SCCP communication.
• PD Responses: How multiple PDs respond via SCCP can vary based on implementation or specific protocol rules within SCCP for multi-drop environments:
  • Highest Class Prevails: A common approach is that all PDs might listen, but the protocol might dictate that the device requiring the highest power class effectively communicates that requirement to the PSE. The PSE then budgets for this highest requirement for the entire segment.
  • Combined/Aggregated Request: Devices might coordinate or the protocol might define a way to signal the total power needed for the segment.
  • First Responder: Sometimes, only the first PD might be designated to handle the SCCP classification on behalf of the segment, potentially relaying the highest requirement it knows of from downstream devices (though this requires more complex intra-device communication).
• PSE Allocation: The PSE receives the SCCP information (representing the segment's needs) and allocates power accordingly. It must budget enough power for the sum of all devices, considering the classification result. If the requested power exceeds the PSE's capability, it might deny power or provide a lower class if acceptable.

3. Power-Up and Operation in a Daisy Chain:

• PSE Applies Power: Based on successful detection and classification, the PSE applies the main PoDL operating voltage (e.g., 24V, 48V, etc., depending on the PoDL class and system design).
• Power Pass-Through: This is the key hardware feature for daisy-chain PoDL.
  • PD1 receives power on its "input" port.
  • It uses internal power regulation (e.g., a DC-DC converter) to power its own circuitry.
  • Crucially, it also includes pass-through circuitry (often using low-resistance MOSFETs) that connects its power input lines to its "output" port lines.
  • This allows the PoDL DC power, minus what PD1 consumed, to flow onwards to PD2.
• Sequential Powering: PD2 receives power from PD1's output, powers itself, and passes the remainder to PD3, and so on down the chain.
• Voltage Drop: This is a major limitation. Each PD's pass-through circuit introduces a small voltage drop, and each cable segment between devices adds resistance, causing further voltage drop (V = I * R). The PSE must supply a high enough voltage initially so that the last device (PDn) in the chain still receives a voltage above its minimum operating threshold.
• Current Summation: The total current drawn from the PSE is the sum of the currents consumed by PD1, PD2, ..., PDn. The PSE must be capable of supplying this total current within the allocated power class limits.

Hardware Considerations for Daisy-Chain PDs:

• Dual Ports: Obvious physical requirement for input and output.
• Detection Circuit: Standard PoDL detection signature circuit on the input.
• SCCP Logic: Capable of participating in multi-drop SCCP communication as defined by the standard/implementation.
• Internal Power Regulation: To power the device itself from the PoDL input.
• Power Pass-Through Circuit: Low-impedance switching (e.g., MOSFETs) to efficiently pass power from input to output terminals with minimal voltage drop. This circuitry needs to be managed by the PD's controller.

Robustness: Must handle potential downstream faults (e.g., provide some protection if the output port is shorted). 

I wonder if it can be also connected with line termination (even without powering) - only end/edge devices should terminate the line (problem not present in point-to-point T1L), so every reconfiguration could involve some means of dynamic termination and a way of detecting if we are in the middle or at the end of the segment?  

From the little I understand, I believe there would have to be some form of line termination in the PD controller device, which the PSE evaluates upon power up. TI have some great application notes that I've found useful.

https://www.ti.com/lit/an/snvaa74/snvaa74.pdf?ts=1743926633636

https://www.ti.com/lit/ab/snla395/snla395.pdf?ts=1743885145439

The other thing I don't quite follow is Sleep Mode. I don't think that'll work in a daisy chain config. If you had say 10 nodes 5 meters apart, in multihop system, I cannot quite see how 3V3 would power all 10 devices in sleep mode.

From the little I understand, I believe there would have to be some form of line termination in the PD controller device, which the PSE evaluates upon power up. TI have some great application notes that I've found useful.

https://www.ti.com/lit/an/snvaa74/snvaa74.pdf?ts=1743926633636

https://www.ti.com/lit/ab/snla395/snla395.pdf?ts=1743885145439

The other thing I don't quite follow is Sleep Mode. I don't think that'll work in a daisy chain config. If you had say 10 nodes 5 meters apart, in multihop system, I cannot quite see how 3V3 would power all 10 devices in sleep mode.