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  • Author Author: embeddedguy
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PCB designing with Autodesk Fusion 360

embeddedguy

Most of us who like to make PCBs are familiar with Eagle CAD drawing software. I started using EAGLE when it was taught in my university during my bachelors degree. At that time I did not even realize that PCB designing skills would be very useful to me in the future even after years of passing out.

But some time ago Autodesk announce that it will discontinue EAGLE from somewhere in the mid of 2027. That was a bit shocking news for me who used EAGLE to design some PCBs.

But recently I gave found that Autodesk Fusion 360 for personal use is cloud-based development platform also to design PCBs, with similar features as EAGLE has. It is free to use for personal use and has limited features. BTW the full feature version comes at $ 85/month or $ 768/year plan.

For now, I just give it a try to Fusion for personal user. Here is a 2-layer PCB layout design. I personally found Fusion 360 for PCB easy to use and it has some nice features that helps developer to create complex PCB. 

What do you think? Let me know in the comments,

image

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  • Just pasting the dev-kit Gerber file screenshots here, so it's easier to compare if you're making any modifications to your layout. 

    I think if you don't need all GPIO, it would be preferable to eliminate some, if it means you'll get a fuller ground plane. The screenshot below only shows about 7 signals on the bottom layer, plus a power connection, so if you can skip 7 GPIO, maybe that could help a lot. Of course, if you need that GPIO, then this won't be an option : (

    Top:

    image

    Bottom:

    image

    Inner 1:

    image

    Inner 2:

    image

  • in reply to shabaz

    Right, thanks for posting the above screenshots. BTW I have to say that the actual dev kit size of a lot larger than my board which has only 23x33 in size. The GPIOS that I would need are somewhat kind of mandatory for my design. First I need SPI to connect some more devices when I want, Then I need some debug pins from JTAG standar and SWDIO and SWDCLK. After that I need atleast one Analog input pin. Then I need two RTC peripheral pins for my design to connect RTC for low power design that Nordic is known for. Then I can maybe skip those NFC pins.!

    Right now, I am more doing those ANT trace impedance matching design. So if you would see the schematic, I have ANT pin and then matching circuit to the antenna and then in the layout I have N$15 which is connected to the antenna pin towards the antenna.

    image

    image

    I am using the following following suggestions from AppCad

    image

  • in reply to shabaz

    All those separate GND islands are connected with VIAs.

  • in reply to embeddedguy

    Hi! I understand that, but what I mean is that the ground path needs to follow the RF signal path all the way back to the IC. It shouldn't deviate and have to travel through other portions of the PCB through multiple vias if that is happening.

    Since there's no full ground plane, that path needs to be checked and corrected (I can't work that path out, it's hard to do visually).

  • in reply to embeddedguy

    Agree, they explicitly call that out in the datasheet too.

  • in reply to shabaz

    Ok. Let me clarify that thing again.  So, on the top layer I have GND plane around the track that leads to the ANT. As the below.(N$15 till N$6) is the track.

    image

    On the bottom layer there is entire GND plane that is from the pin on the SoC to the Antenna. As below for the same track.

    image

    Is there anything that I am missing here? I understand that these separate planes are connected to each other with tracks and VIAs as well.

    For the SoC pad that is also connected using Vias to the bottom GND layer as pointed by you in the dev kits and also as seen in above pictures, when I try to do that there is a error of Overlap (SMD-VIA). I need to find the workaround for that. 

  • in reply to embeddedguy

    (Mobile so I can't type much).

    The issue is this bit:

    "On the bottom layer there is entire GND plane that is from the pin on the SoC to the Antenna".

    Although there is copper there as you say, it doesn't actually connect to the IC except after having gone further around the board hopping between vias, until it reaches a single via near the top-left of the IC (I colored that in green in an earlier comment). Via holes under the IC will help with that (they were not present in the Gerber files I looked at.).  It needs to connect very close to the RF trace, instead of having to go around the board as mentioned.

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  • in reply to embeddedguy

    (Mobile so I can't type much).

    The issue is this bit:

    "On the bottom layer there is entire GND plane that is from the pin on the SoC to the Antenna".

    Although there is copper there as you say, it doesn't actually connect to the IC except after having gone further around the board hopping between vias, until it reaches a single via near the top-left of the IC (I colored that in green in an earlier comment). Via holes under the IC will help with that (they were not present in the Gerber files I looked at.).  It needs to connect very close to the RF trace, instead of having to go around the board as mentioned.

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