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  • Author Author: Jan Cumps
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Renesas Solution Starter Kit for RX23E-A - break out the SPI signals

Jan Cumps

I'm about to design some analogue measurement devices based on the Renesas RX23E-A controller. With SPI as communication channel between that IC and a more generic communication/processing board.

The full design of the future project is still settling. Most likely it 'll have the RX23 do the analogue duties. Another controller (or SOB?) doing the data handling and communication. Isolation between the two for power and communication. What I want to try now, is to set up a decent RX23 architecture. Hardware and software. At this time: can I create firmware that uses the RX23 to do high fidelity sampling, and exchange data via SPI (act as a SPI client).

I have an evaluation board from Road test: Renesas Solution Starter Kit for RX23E-A. It has options for USB, CAN and RS-485/profibus. Out of box, it doesn't expose SPI. But it has the capabilities to do so. This blog shows a few modifications I did to get at the SPI signals.

The application note for this kit shows what I can get at without needing bodge wires. The connector J3 exposes a number of communication lines. Including ones needed to use the SPI peripheral. But several of them are connected to the SPI and profibus ICs. So i need to do a few little changes.

image

I've been checking all options for the SPI signals:

image

and here's what I selected:

image

On the PCB, I need to mount J3, and remove R90 and R28. The resistors are 0402 and 0603. Doable when careful.

image

Before:
image

After:

image

Not so difficult with this kit. The two resistors have enough space to work on them. I used a decent flat solder tip and shoved them off their pads. J3 is a standard pin header. Easy to solder, if you use enough power for the pins that are connected to the power planes. I taped the resistors on a piece of paper and put them inside the kit's box. In case I want to restore it to its original configuration.

All set to start checking if I can write decent firmware ...

  • in reply to Jan Cumps

    Very helpful info for this microcontroller. SPI slave with DMA is highly important functionality if the RX23E-A is going to be used for its analog capabilities with an external processor. Looking forward to seeing the solution take shape!

  • Progress: I have a PI Pico running as SPI master, and the Renesas RX23E-A as SPI slave. 1 Mbps. Both sides with DMA support.

    image

    image

    RX23E-A source

    /**********************************************************************************************************************
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
* applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS
* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
* this software. By using this software, you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
*
* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
**********************************************************************************************************************/
/**********************************************************************************************************************
* File Name    : rx231_rsk_rspi_slave_sample.c
* Device(s)    : RX Family
* Tool-Chain   : Renesas RX Standard Toolchain
* OS           : None
* H/W Platform : RSKRX231 for demo
* Description  : Simple demonstration for using the RSPI API.
***********************************************************************************************************************
* History : DD.MM.YYYY Version Description
*           10.09.2020 1.00    Initial Release
**********************************************************************************************************************/

/**********************************************************************************************************************
Includes   <System Includes> , "Project Includes"
**********************************************************************************************************************/
#include <stdio.h>              /* For sprintf */
#include "platform.h"           /* Located in the FIT BSP module */
#include "r_rspi_rx_pinset.h"
#include "r_rspi_rx_if.h"       /* The RSPI module API interface file. */

#define RSPI_DMAC_TEST (0)
#define RSPI_DTC_TEST  (0)

#if RSPI_DTC_TEST == (1)
#include "r_dtc_rx_if.h"
#endif

#if RSPI_DMAC_TEST == (1)
#include "r_dmaca_rx_if.h"
#endif

#if RSPI_CFG_LONGQ_ENABLE == 1
#include "r_longq_if.h"
#endif
/* RSPI_CFG_LONGQ_ENABLE */


/**********************************************************************************************************************
Macro definitions
**********************************************************************************************************************/
#define DEMO_DATA_SIZE  (32)
#define RSPI_CFG_USE_GPIO_SSL (0) /* Use RSPI to control the slave select. */
#define RSPI_CHANNEL        (0)
#define LOOP_COUNT     (5)

#if RSPI_CFG_USE_GPIO_SSL == (1)
#define RSPI_CFG_SS_GPIO_PIDR   PORTA.PIDR.BIT.B4
#define PORT_LOW    (0)
#define PORT_HIGH   (1)
#endif

#if RSPI_CFG_LONGQ_ENABLE == 1
#define RSPI_USER_LONGQ_IGN_OVERFLOW    (1)             /* Ignore_overflow of error log buffer. */
#define USER_DRIVER_ID                  (1)
#define USER_LOG_MAX                    (63)
#define USER_LOG_ADR_MAX                (0x00001fff)
#endif /* RSPI_CFG_LONGQ_ENABLE */

#define SPI_DATA_TYPE uint8_t
#define SPI_DATA_SIZE RSPI_SPCMD_BIT_LENGTH_8



/**********************************************************************************************************************
Private global variables and functions
**********************************************************************************************************************/
#if RSPI_CFG_LONGQ_ENABLE == 1
static longq_hdl_t     p_rspi_user_long_que;                            /* LongQ handler        */
extern uint32_t R_COM_MTL_Get_BufferAddress(void);
#endif /* RSPI_CFG_LONGQ_ENABLE */

static void my_rspi_callback(void *p_data);
static bool verify_data(SPI_DATA_TYPE * p_data_source, SPI_DATA_TYPE * p_data_dest, uint16_t length);
static void rspi_rx231_init_ports(void);
static void init_demo_data(void);
static void tst_trap(void);
#if RSPI_CFG_USE_GPIO_SSL == (1)
void poll_port(uint8_t level);
#endif
static volatile bool  transfer_busy = false;

static SPI_DATA_TYPE  demo_data_source[DEMO_DATA_SIZE] = {0};
static SPI_DATA_TYPE  demo_data_dest[DEMO_DATA_SIZE] = {0};
/* Define for RSPI Information structure type */
typedef struct
{
    uint32_t  data_cnt;                   // Number of data (byte unit)
    uint8_t * p_tx_data;                  // Pointer to transmit data buffer
    uint8_t * p_rx_data;                  // Pointer to receive data buffer
} rspi_info_t;
rspi_info_t demo_data_test;
static rspi_evt_t demo_callback_event; // Storage for callback result data.

/* Initialize demo command word settings.
 * This can be constant if you don't need to change the settings. */
static rspi_command_word_t my_rspi_command;

static rspi_err_t           my_rspi_err;
static rspi_handle_t        my_rspi_handle;
static rspi_chnl_settings_t my_rspi_setting;
static uint32_t             my_version;
static uint8_t              version_str[12] = {0}; // Enough space to hold the formatted version string.
static uint32_t             loop_count = 0;

#if RSPI_DTC_TEST == (1)
static volatile uint32_t       transfer_data[4];
static volatile uint32_t       receive_data[4];
#endif

/**********************************************************************************************************************
* Function Name: tst_trap
* Description  : It's a trap function
* Arguments    : None
* Return Value : None
**********************************************************************************************************************/
static void tst_trap(void)
{
#if RSPI_CFG_LONGQ_ENABLE == 1
    longq_err_t         err;

    /* Set last error log to buffer. */
    R_RSPI_Log(USER_DRIVER_ID, USER_LOG_MAX, USER_LOG_ADR_MAX);

    /* Close LONGQ module. */
    err = R_LONGQ_Close(p_rspi_user_long_que);
    if (LONGQ_SUCCESS != err)
    {
        while(1)
        {
            /* Infinite Loop */
        }
    }
#endif
    /* RSPI_CFG_LONGQ_ENABLE */
    while(1){/*Do nothing*/}
}
/* End of function tst_trap. */

#if RSPI_DMAC_TEST == (1)
/**********************************************************************************************************************
* Outline      : DMAC callback function
* Function Name: DMA_CallBack_W
* Description  : It's the RSPI transmit end callback function via DMAC.
* Arguments    : none
* Return Value : none
**********************************************************************************************************************/
void DMA_CallBack_W(void)
{
    volatile dmaca_return_t    ret_dmaca;
    dmaca_stat_t               p_stat_dmaca;

    my_rspi_handle->channel = RSPI_CHANNEL;

    /* check DMA end */
    ret_dmaca = R_DMACA_Control(DMACA_CH0, DMACA_CMD_STATUS_GET, (dmaca_stat_t*)&p_stat_dmaca);
    if (DMACA_SUCCESS != ret_dmaca)
    {
        return;
    }

    if (false != (p_stat_dmaca.dtif_stat))
    {
        ret_dmaca = R_DMACA_Control(DMACA_CH0, DMACA_CMD_DTIF_STATUS_CLR, (dmaca_stat_t*)&p_stat_dmaca);
        R_RSPI_DisableSpti(my_rspi_handle);
        R_RSPI_IntSptiIerClear(my_rspi_handle);
    }

    if (false != (p_stat_dmaca.esif_stat))
    {
        ret_dmaca = R_DMACA_Control(DMACA_CH0, DMACA_CMD_ESIF_STATUS_CLR, (dmaca_stat_t*)&p_stat_dmaca);
    }

    return;
}
/* End of function DMA_CallBack_W. */

/**********************************************************************************************************************
* Outline      : DMAC callback function
* Function Name: DMA_CallBack_R
* Description  : It's the RSPI receive end callback function via DMAC.
* Arguments    : none
* Return Value : none
**********************************************************************************************************************/
void DMA_CallBack_R(void)
{
    volatile dmaca_return_t    ret_dmaca;
    dmaca_stat_t               p_stat_dmaca;

    my_rspi_handle->channel = RSPI_CHANNEL;

    /* check DMA end */
    ret_dmaca = R_DMACA_Control(DMACA_CH1, DMACA_CMD_STATUS_GET, (dmaca_stat_t*)&p_stat_dmaca);
    if (DMACA_SUCCESS != ret_dmaca)
    {
        return;
    }

    if (false != (p_stat_dmaca.dtif_stat))
    {
        ret_dmaca = R_DMACA_Control(DMACA_CH1, DMACA_CMD_DTIF_STATUS_CLR, (dmaca_stat_t*)&p_stat_dmaca);
        R_RSPI_IntSpriIerClear(my_rspi_handle);
        R_RSPI_DisableRSPI(my_rspi_handle);
    }

    if (false != (p_stat_dmaca.esif_stat))
    {
        ret_dmaca = R_DMACA_Control(DMACA_CH1, DMACA_CMD_ESIF_STATUS_CLR, (dmaca_stat_t*)&p_stat_dmaca);
    }

    transfer_busy = false;
    return;
}
/* End of function DMA_CallBack_R. */

/**********************************************************************************************************************
* Outline      : Enable DMAC for RSPI transmission
* Function Name: r_dmaca_set_send
* Description  : Enables DMAC for RSPI transmission.
* Arguments    : dmaca_transfer_data_cfg_t  * p_data_cfg        ; Contains the settings for Transfer data
*              : void                       * source_data       ; Source data address
*              : uint32_t                   data_len            ; Data length
*              : uint32_t                   reg_buff            ; Pointer of transmit data buffer
*              : dmaca_activation_source_t  act_source          ; DMAC activation source
* Return Value : none
**********************************************************************************************************************/
static void r_dmaca_set_send(dmaca_transfer_data_cfg_t *p_data_cfg, void *source_data, uint32_t data_len,
                             uint32_t reg_buff, dmaca_activation_source_t act_source)
{
    p_data_cfg->transfer_mode         = DMACA_TRANSFER_MODE_NORMAL;
    p_data_cfg->repeat_block_side     = DMACA_REPEAT_BLOCK_DESTINATION;
    p_data_cfg->data_size             = DMACA_DATA_SIZE_LWORD;

    p_data_cfg->act_source            = act_source;
    p_data_cfg->request_source        = DMACA_TRANSFER_REQUEST_PERIPHERAL;
    p_data_cfg->dtie_request          = DMACA_TRANSFER_END_INTERRUPT_ENABLE;
    p_data_cfg->esie_request          = DMACA_TRANSFER_ESCAPE_END_INTERRUPT_DISABLE;
    p_data_cfg->rptie_request         = DMACA_REPEAT_SIZE_END_INTERRUPT_DISABLE;
    p_data_cfg->sarie_request         = DMACA_SRC_ADDR_EXT_REP_AREA_OVER_INTERRUPT_DISABLE;
    p_data_cfg->darie_request         = DMACA_DES_ADDR_EXT_REP_AREA_OVER_INTERRUPT_DISABLE;

    p_data_cfg->src_addr_mode         = DMACA_SRC_ADDR_INCR;
    p_data_cfg->des_addr_mode         = DMACA_DES_ADDR_FIXED;

    p_data_cfg->src_addr_repeat_area  = DMACA_SRC_ADDR_EXT_REP_AREA_NONE;
    p_data_cfg->des_addr_repeat_area  = DMACA_DES_ADDR_EXT_REP_AREA_NONE;
    p_data_cfg->interrupt_sel         = DMACA_CLEAR_INTERRUPT_FLAG_BEGINNING_TRANSFER;

    /* The side being repeat or block in repeat / block transfer mode */
    p_data_cfg->p_src_addr            = source_data;
    p_data_cfg->p_des_addr            = (void *)reg_buff;
    p_data_cfg->transfer_count        = data_len;
}
/* End of function r_dmaca_set_send. */

/**********************************************************************************************************************
* Outline      : Enable DMAC for RSPI reception
* Function Name: r_dmaca_set_recv
* Description  : Enables DMAC for RSPI reception.
* Arguments    : dmaca_transfer_data_cfg_t  * p_data_cfg        ; Contains the settings for Transfer data
*              : void                       * dest_data         ; Destination data address
*              : uint32_t                   data_len            ; Destination data length
*              : uint32_t                   reg_buff            ; Pointer of receive data buffer
*              : dmaca_activation_source_t  act_source          ; DMAC activation source
* Return Value : none
**********************************************************************************************************************/
static void r_dmaca_set_recv(dmaca_transfer_data_cfg_t *p_data_cfg, void *dest_data, uint32_t data_len,
                             uint32_t reg_buff, dmaca_activation_source_t act_source)
{
    p_data_cfg->transfer_mode         = DMACA_TRANSFER_MODE_NORMAL;
    p_data_cfg->repeat_block_side     = DMACA_REPEAT_BLOCK_DESTINATION;
    p_data_cfg->data_size             = DMACA_DATA_SIZE_LWORD;

    p_data_cfg->act_source            = act_source;
    p_data_cfg->request_source        = DMACA_TRANSFER_REQUEST_PERIPHERAL;
    p_data_cfg->dtie_request          = DMACA_TRANSFER_END_INTERRUPT_ENABLE;
    p_data_cfg->esie_request          = DMACA_TRANSFER_ESCAPE_END_INTERRUPT_DISABLE;
    p_data_cfg->rptie_request         = DMACA_REPEAT_SIZE_END_INTERRUPT_DISABLE;
    p_data_cfg->sarie_request         = DMACA_SRC_ADDR_EXT_REP_AREA_OVER_INTERRUPT_DISABLE;
    p_data_cfg->darie_request         = DMACA_DES_ADDR_EXT_REP_AREA_OVER_INTERRUPT_DISABLE;

    p_data_cfg->src_addr_mode         = DMACA_SRC_ADDR_FIXED;
    p_data_cfg->des_addr_mode         = DMACA_DES_ADDR_INCR;

    p_data_cfg->src_addr_repeat_area  = DMACA_SRC_ADDR_EXT_REP_AREA_NONE;
    p_data_cfg->des_addr_repeat_area  = DMACA_DES_ADDR_EXT_REP_AREA_NONE;
    p_data_cfg->interrupt_sel         = DMACA_CLEAR_INTERRUPT_FLAG_BEGINNING_TRANSFER;

    /* The side being repeat or block in repeat / block transfer mode */
    p_data_cfg->p_src_addr            = (void *)reg_buff;
    p_data_cfg->p_des_addr            = dest_data;
    p_data_cfg->transfer_count        = data_len;
}
/* End of function r_dmaca_set_recv. */
#endif

#if RSPI_DTC_TEST == (1)
/**********************************************************************************************************************
* Outline      : Enable DTC for RSPI reception
* Function Name: r_dtc_set_recv
* Description  : Enables DTC for RSPI reception.
* Arguments    : dtc_transfer_data_cfg_t    * p_data_cfg        ; Contains the settings for Transfer data
*              : void                       * dest_data         ; Destination data address
*              : uint32_t                   data_len            ; Destination data length
*              : uint32_t                   * p_reg_buff        ; Pointer of receive data buffer
* Return Value : none
**********************************************************************************************************************/
static void r_dtc_set_recv(dtc_transfer_data_cfg_t  *p_data_cfg, void *dest_data, uint32_t data_len,
                           uint32_t *p_reg_buff)
{
    p_data_cfg->transfer_mode          = DTC_TRANSFER_MODE_NORMAL;          // DTC transfer mode
    p_data_cfg->data_size              = DTC_DATA_SIZE_LWORD;               // The size of data
    p_data_cfg->src_addr_mode          = DTC_SRC_ADDR_FIXED;                // Address mode of source
    p_data_cfg->chain_transfer_enable  = DTC_CHAIN_TRANSFER_DISABLE;        // Chain transfer is enabled or not
    p_data_cfg->chain_transfer_mode    = DTC_CHAIN_TRANSFER_CONTINUOUSLY;   // How chain transfer is performed
    p_data_cfg->response_interrupt     = DTC_INTERRUPT_AFTER_ALL_COMPLETE;  // How response interrupt is raised
    /* The side being repeat or block in repeat / block transfer mode */
    p_data_cfg->repeat_block_side      = DTC_REPEAT_BLOCK_DESTINATION;
    p_data_cfg->dest_addr_mode         = DTC_DES_ADDR_INCR;                 // Address mode of destination
    p_data_cfg->source_addr            = (uint32_t)(*p_reg_buff);
                                                                            // Start address of source
    p_data_cfg->dest_addr              = (uint32_t)dest_data;
                                                                            // Start address of destination
    p_data_cfg->transfer_count         = data_len;                          // Transfer count
}
/* End of function r_dtc_set_recv. */

/**********************************************************************************************************************
* Outline      : Enable DTC for RSPI transmission
* Function Name: r_dtc_set_send
* Description  : Enables DTC for RSPI transmission.
* Arguments    : dtc_transfer_data_cfg_t    * p_data_cfg        ; Contains the settings for Transfer data
*              : void                       * source_data       ; Source data address
*              : uint32_t                   data_len            ; Source data length
*              : uint32_t                   * p_reg_buff        ; Pointer of transmit data buffer
* Return Value : none
**********************************************************************************************************************/
static void r_dtc_set_send(dtc_transfer_data_cfg_t  *p_data_cfg, void *source_data, uint32_t data_len,
                           uint32_t *p_reg_buff)
{
    p_data_cfg->transfer_mode         = DTC_TRANSFER_MODE_NORMAL;           // DTC transfer mode
    p_data_cfg->data_size             = DTC_DATA_SIZE_LWORD;                // The size of data
    p_data_cfg->src_addr_mode         = DTC_SRC_ADDR_INCR;                  // Address mode of source
    p_data_cfg->chain_transfer_enable = DTC_CHAIN_TRANSFER_DISABLE;         // Chain transfer is enabled or not
    p_data_cfg->chain_transfer_mode   = DTC_CHAIN_TRANSFER_CONTINUOUSLY;    // How chain transfer is performed
    p_data_cfg->response_interrupt    = DTC_INTERRUPT_AFTER_ALL_COMPLETE;   // How response interrupt is raised
    /* The side being repeat or block in repeat / block transfer mode */
    p_data_cfg->repeat_block_side     = DTC_REPEAT_BLOCK_DESTINATION;
    p_data_cfg->dest_addr_mode        = DTC_DES_ADDR_FIXED;                 // Address mode of destination
    p_data_cfg->source_addr           = (uint32_t)source_data;
                                                                            // Start address of source
    p_data_cfg->dest_addr             = (uint32_t)(*p_reg_buff);            // Start address of destination
    p_data_cfg->transfer_count        = data_len;                           // Transfer count
}
/* End of function r_dtc_set_send. */
#endif


/**********************************************************************************************************************
* Function Name: main
* Description  : Main loop for slave sample application.
*                This sample application and the Master sample application implement Master-Slave communication together.
*                The sample application simulates Slave receiving and sending data in Master-Slave communication,
*                and finally compares whether the received data is consistent with expectations.
*                The RSPI module version number is retrieved and can be displayed on the Renesas Virtual Debug Console
*                window if desired.
*
* Operation    : 1) RSPCKA, MOSIA, MISOA, SSLA0 of the Master are connected with RSPCKA, MOSIA, MISOA, SSLA0 of
*                   the Slave respectively. RSKRX65N is the Master and RSKRX231 is the Slave as an example:
*                                   RSKRX65N               RSKRX231
*                    RSPCKA         JA3-Pin6               J3-Pin15
*                    MOSIA          JA3-Pin7               J3-Pin14
*                    MISOA          JA3-Pin8               J3-Pin13
*                    SSLA0          JA3-Pin5               J3-Pin16
*                2) Build and download this sample application to the RSK board using the e2studio debugger.
*                3) Select the Renesas Virtual Debug Console view in e2studio to view printf information.
*                4) Run this application in this debugger, and then run the Master application in the Master debugger.
*                5) Observe the version number print in the debug console window.
*                6) Perform multiple times Slave Read then Slave Write processing. First output how many times this
*                   processing is (counting from 0). If the data read every time is consistent with expectations,
*                   it will output "Success!". otherwise, it will output "Failed."
*
* Arguments    : None
* Return Value : None
**********************************************************************************************************************/
void main(void)
{
    my_rspi_command.cpha          = RSPI_SPCMD_CPHA_SAMPLE_EVEN;
    my_rspi_command.cpol          = RSPI_SPCMD_CPOL_IDLE_LO;
    my_rspi_command.br_div        = RSPI_SPCMD_BR_DIV_1;
    my_rspi_command.ssl_assert    = RSPI_SPCMD_ASSERT_SSL0;
    my_rspi_command.ssl_negate    = RSPI_SPCMD_SSL_KEEP;
//    my_rspi_command.bit_length    = RSPI_SPCMD_BIT_LENGTH_32;
    my_rspi_command.bit_length    = SPI_DATA_SIZE;
    my_rspi_command.bit_order     = RSPI_SPCMD_ORDER_MSB_FIRST;
    my_rspi_command.next_delay    = RSPI_SPCMD_NEXT_DLY_SSLND;
    my_rspi_command.ssl_neg_delay = RSPI_SPCMD_SSL_NEG_DLY_SSLND;
    my_rspi_command.clock_delay   = RSPI_SPCMD_CLK_DLY_SPCKD;
    my_rspi_command.dummy         = RSPI_SPCMD_DUMMY;

#if RSPI_DMAC_TEST == (1)
    dmaca_transfer_data_cfg_t   p_data_cfg_dmac;
    dmaca_transfer_data_cfg_t   p_data_cfg_dmac_r;
    dmaca_return_t              ret_dmaca;
    dmaca_stat_t                p_stat_dmaca;
    dmaca_stat_t                p_stat_dmaca_r;
    uint32_t                    reg_buff;
    rspi_err_t                  Ret;
    my_rspi_handle->channel = RSPI_CHANNEL;
#endif

#if RSPI_DTC_TEST == (1)
    uint32_t                    chain_transfer_nr;
    dtc_activation_source_t     act_source_w;
    dtc_transfer_data_cfg_t     p_data_cfg_w;
    dtc_cmd_arg_t               p_args_w;
    dtc_activation_source_t     act_source_r;
    dtc_transfer_data_cfg_t     p_data_cfg_r;
    dtc_cmd_arg_t               p_args_r;
    dtc_err_t                   ret_dtc;
    uint32_t                    reg_buff;
    rspi_err_t                  Ret;
    my_rspi_handle->channel = RSPI_CHANNEL;
#endif

    /* Get module software version using the API function provided. */
    my_version = R_RSPI_GetVersion();

    /* Demonstrate parsing and formatting of version number. */
    sprintf((char *)version_str, "RSPI v%1.0hu.%2.2hu\r\n", ((my_version >> 16)&0xf), (my_version & 0xff));
    printf((char *)version_str); // View stdout in the Renesas Virtual Debug Console window.

    init_demo_data(); // Prepare demo data buffers.
    /* Initialize I/O port pins for use with the RSPI peripheral.
     * This is specific to the MCU and ports chosen. */
    rspi_rx231_init_ports();
#if RSPI_CFG_USE_GPIO_SSL == (1)
    poll_port(PORT_HIGH);
#endif
#if RSPI_CFG_USE_GPIO_SSL == (1)
    poll_port(PORT_LOW);
#endif
    /* Configure the RSPI settings structure  */
    my_rspi_setting.bps_target = 1000000;                    // Ask for 1Mbps bit-rate.
//    my_rspi_setting.bps_target = 250000;                    // Ask for 1Mbps bit-rate.
    my_rspi_setting.master_slave_mode = RSPI_MS_MODE_SLAVE;  // Configure the RSPI as SPI Master.
#if RSPI_CFG_USE_GPIO_SSL == (0)
    my_rspi_setting.gpio_ssl = RSPI_IF_MODE_4WIRE;           // Set interface mode to 4-wire.
#else
    my_rspi_setting.gpio_ssl = RSPI_IF_MODE_3WIRE;           // Set interface mode to 3-wire.
#endif /* RSPI_CFG_USE_GPIO_SSL == (0) */
#if RSPI_DMAC_TEST == (1)
    my_rspi_setting.tran_mode = RSPI_TRANS_MODE_DMAC;
#endif
#if RSPI_DTC_TEST == (1)
    my_rspi_setting.tran_mode = RSPI_TRANS_MODE_DTC;
#endif
    /* Open the RSPI channel using the API function */
    my_rspi_err = R_RSPI_Open (0,                   // RSPI channel number
                               &my_rspi_setting,    // Address of the RSPI settings structure.
                               my_rspi_command,
                               &my_rspi_callback,   // Address of user-defined callback function.
                               &my_rspi_handle);    // Address of where the handle is to be stored

    /* If there were an error this would demonstrate error detection of API calls. */
    if (RSPI_SUCCESS != my_rspi_err)
    {
        tst_trap(); // Your error handling code would go here.
    }

    /* Demonstrate Slave read then Slave write processing. */
    while (loop_count < LOOP_COUNT)
    {
        transfer_busy = true;  // Prepare a flag for polling of the transfer status.

#if RSPI_DMAC_TEST == (1)
        /* === DMAC Enable  === */
        Ret = R_RSPI_GetBuffRegAddress(my_rspi_handle, &reg_buff);
        if (RSPI_SUCCESS > Ret)
        {
           tst_trap();
        }

        R_DMACA_Init();

        ret_dmaca = R_DMACA_Open(DMACA_CH0);
        if (DMACA_SUCCESS != ret_dmaca)
        {
            tst_trap();
        }

        ret_dmaca = R_DMACA_Open(DMACA_CH1);
        if (DMACA_SUCCESS != ret_dmaca)
        {
            tst_trap();
        }

        ret_dmaca = R_DMACA_Int_Callback(DMACA_CH0, DMA_CallBack_W);
        if (DMACA_SUCCESS != ret_dmaca)
        {
            tst_trap();
        }

        ret_dmaca = R_DMACA_Int_Callback(DMACA_CH1, DMA_CallBack_R);
        if (DMACA_SUCCESS != ret_dmaca)
        {
            tst_trap();
        }
        ret_dmaca = R_DMACA_Int_Enable(DMACA_CH0, 10);
        if (DMACA_SUCCESS != ret_dmaca)
        {
            tst_trap();
        }
        ret_dmaca = R_DMACA_Int_Enable(DMACA_CH1, 10);
        if (DMACA_SUCCESS != ret_dmaca)
        {
            tst_trap();
        }
        r_dmaca_set_send(&p_data_cfg_dmac, &demo_data_source, DEMO_DATA_SIZE, reg_buff, IR_RSPI0_SPTI0);
        r_dmaca_set_recv(&p_data_cfg_dmac_r, &demo_data_dest, DEMO_DATA_SIZE, reg_buff, IR_RSPI0_SPRI0);

        ret_dmaca = R_DMACA_Create(DMACA_CH0, (dmaca_transfer_data_cfg_t *)&p_data_cfg_dmac);
        if (DMACA_SUCCESS != ret_dmaca)
        {
            tst_trap();
        }

        ret_dmaca = R_DMACA_Create(DMACA_CH1, (dmaca_transfer_data_cfg_t *)&p_data_cfg_dmac_r);
        if (DMACA_SUCCESS != ret_dmaca)
        {
            tst_trap();
        }

        ret_dmaca = R_DMACA_Control(DMACA_CH0, DMACA_CMD_ENABLE, (dmaca_stat_t*)&p_stat_dmaca);
        if (DMACA_SUCCESS != ret_dmaca)
        {
            tst_trap();
        }

        ret_dmaca = R_DMACA_Control(DMACA_CH1, DMACA_CMD_ENABLE, (dmaca_stat_t*)&p_stat_dmaca_r);
        if (DMACA_SUCCESS != ret_dmaca)
        {
            tst_trap();
        }
#endif

#if RSPI_DTC_TEST == (1)
        /* === DTC Enable === */
        Ret = R_RSPI_GetBuffRegAddress(my_rspi_handle, &reg_buff);
        if (RSPI_SUCCESS > Ret)
        {
           tst_trap();
        }

        ret_dtc = R_DTC_Open();
        if (DTC_SUCCESS != ret_dtc)
        {
            tst_trap();
        }

        act_source_w         = DTCE_RSPI0_SPTI0;
        act_source_r         = DTCE_RSPI0_SPRI0;
        r_dtc_set_send(&p_data_cfg_w, demo_data_source, DEMO_DATA_SIZE, &reg_buff);
        r_dtc_set_recv(&p_data_cfg_r, demo_data_dest,DEMO_DATA_SIZE, &reg_buff);
        chain_transfer_nr   = 0;

        ret_dtc = R_DTC_Create(act_source_w,
                               (dtc_transfer_data_t *)&transfer_data[0],
                               (dtc_transfer_data_cfg_t *)&p_data_cfg_w,
                               chain_transfer_nr);
        if (DTC_SUCCESS != ret_dtc)
        {
            tst_trap();
        }

        ret_dtc = R_DTC_Create(act_source_r,
                               (dtc_transfer_data_t *)&receive_data[0],
                               (dtc_transfer_data_cfg_t *)&p_data_cfg_r,
                               chain_transfer_nr);
        if (DTC_SUCCESS != ret_dtc)
        {
            tst_trap();
        }

        p_args_w.chain_transfer_nr = 0;
        p_args_r.chain_transfer_nr = 0;
        p_args_w.act_src           = DTCE_RSPI0_SPTI0;
        p_args_r.act_src           = DTCE_RSPI0_SPRI0;

        ret_dtc = R_DTC_Control(DTC_CMD_ACT_SRC_ENABLE, NULL, (void *)&p_args_w);
        if (DTC_SUCCESS != ret_dtc)
        {
            tst_trap();
        }

        ret_dtc = R_DTC_Control(DTC_CMD_ACT_SRC_ENABLE, NULL, (void *)&p_args_r);
        if (DTC_SUCCESS != ret_dtc)
        {
            tst_trap();
        }

        ret_dtc = R_DTC_Control(DTC_CMD_DTC_START, NULL, NULL);
        if (DTC_SUCCESS != ret_dtc)
        {
            tst_trap();
        }
#endif

        /* Start Slave receive using the API function. */
        my_rspi_err = R_RSPI_Read(my_rspi_handle,
                                  my_rspi_command,
                                  demo_data_dest,
                                  (DEMO_DATA_SIZE));

        if (RSPI_SUCCESS != my_rspi_err) // Check for successful function return.
        {
            tst_trap(); // Your error handling code would go here.
        }

        /* The R_RSPI_Read() function starts the transfer and returns immediately.
         * Your callback function will be caled when the transfer is complete. We are using
         * the callback function here to update the transfer status flag. */
        while (transfer_busy)
        {
            R_BSP_NOP(); // Application could do something useful here while waiting for transfer to complete.
        }

        /* The callback retrieved the operation event result code. */
        if (RSPI_EVT_TRANSFER_COMPLETE != demo_callback_event)
        {
            tst_trap(); // Something unexpected happened.
        }

#if RSPI_DMAC_TEST == (1)
        /* === DMAC Disable === */

        ret_dmaca = R_DMACA_Control(DMACA_CH0, DMACA_CMD_DISABLE, (void *)&p_stat_dmaca);
        if (DMACA_SUCCESS != ret_dmaca)
        {
            tst_trap();
        }
        ret_dmaca = R_DMACA_Control(DMACA_CH1, DMACA_CMD_DISABLE, (void *)&p_stat_dmaca_r);
        if (DMACA_SUCCESS != ret_dmaca)
        {
            tst_trap();
        }
        ret_dmaca = R_DMACA_Close(DMACA_CH0);
        if (DMACA_SUCCESS < ret_dmaca)
        {
            tst_trap();
        }
        ret_dmaca = R_DMACA_Close(DMACA_CH1);
        if (DMACA_SUCCESS < ret_dmaca)
        {
            tst_trap();
        }
#endif

#if RSPI_DTC_TEST == (1)
        /* === DTC Disable === */
        p_args_w.act_src           = DTCE_RSPI0_SPTI0;
        p_args_r.act_src           = DTCE_RSPI0_SPRI0;

        p_args_w.chain_transfer_nr = 0;
        ret_dtc = R_DTC_Control(DTC_CMD_DTC_STOP, NULL, NULL);
        if (DTC_SUCCESS != ret_dtc)
        {
            tst_trap();
        }

        ret_dtc = R_DTC_Control(DTC_CMD_ACT_SRC_DISABLE, NULL, (void *)&p_args_w);
        if (DTC_SUCCESS != ret_dtc)
        {
            tst_trap();
        }

        ret_dtc = R_DTC_Control(DTC_CMD_ACT_SRC_DISABLE, NULL, (void *)&p_args_r);
        if (DTC_SUCCESS != ret_dtc)
        {
            tst_trap();
        }
        ret_dtc = R_DTC_Close();
        if (DTC_SUCCESS != ret_dtc)
        {
            tst_trap();
        }
#endif

        transfer_busy = true;  // Prepare a flag for polling of the transfer status.

#if RSPI_DMAC_TEST == (1)
        /* === DMAC Enable  === */
        Ret = R_RSPI_GetBuffRegAddress(my_rspi_handle, &reg_buff);
        if (RSPI_SUCCESS > Ret)
        {
           tst_trap();
        }

        R_DMACA_Init();

        ret_dmaca = R_DMACA_Open(DMACA_CH0);
        if (DMACA_SUCCESS != ret_dmaca)
        {
            tst_trap();
        }

        ret_dmaca = R_DMACA_Open(DMACA_CH1);
        if (DMACA_SUCCESS != ret_dmaca)
        {
            tst_trap();
        }

        ret_dmaca = R_DMACA_Int_Callback(DMACA_CH0, DMA_CallBack_W);
        if (DMACA_SUCCESS != ret_dmaca)
        {
            tst_trap();
        }

        ret_dmaca = R_DMACA_Int_Callback(DMACA_CH1, DMA_CallBack_R);
        if (DMACA_SUCCESS != ret_dmaca)
        {
            tst_trap();
        }
        ret_dmaca = R_DMACA_Int_Enable(DMACA_CH0, 10);
        if (DMACA_SUCCESS != ret_dmaca)
        {
            tst_trap();
        }
        ret_dmaca = R_DMACA_Int_Enable(DMACA_CH1, 10);
        if (DMACA_SUCCESS != ret_dmaca)
        {
            tst_trap();
        }
        r_dmaca_set_send(&p_data_cfg_dmac, &demo_data_source, DEMO_DATA_SIZE, reg_buff, IR_RSPI0_SPTI0);
        r_dmaca_set_recv(&p_data_cfg_dmac_r, &demo_data_dest, DEMO_DATA_SIZE, reg_buff, IR_RSPI0_SPRI0);

        ret_dmaca = R_DMACA_Create(DMACA_CH0, (dmaca_transfer_data_cfg_t *)&p_data_cfg_dmac);
        if (DMACA_SUCCESS != ret_dmaca)
        {
            tst_trap();
        }

        ret_dmaca = R_DMACA_Create(DMACA_CH1, (dmaca_transfer_data_cfg_t *)&p_data_cfg_dmac_r);
        if (DMACA_SUCCESS != ret_dmaca)
        {
            tst_trap();
        }

        ret_dmaca = R_DMACA_Control(DMACA_CH0, DMACA_CMD_ENABLE, (dmaca_stat_t*)&p_stat_dmaca);
        if (DMACA_SUCCESS != ret_dmaca)
        {
            tst_trap();
        }

        ret_dmaca = R_DMACA_Control(DMACA_CH1, DMACA_CMD_ENABLE, (dmaca_stat_t*)&p_stat_dmaca_r);
        if (DMACA_SUCCESS != ret_dmaca)
        {
            tst_trap();
        }
#endif

#if RSPI_DTC_TEST == (1)
        /* === DTC Enable === */
        Ret = R_RSPI_GetBuffRegAddress(my_rspi_handle, &reg_buff);
        if (RSPI_SUCCESS > Ret)
        {
           tst_trap();
        }

        ret_dtc = R_DTC_Open();
        if (DTC_SUCCESS != ret_dtc)
        {
            tst_trap();
        }

        act_source_w         = DTCE_RSPI0_SPTI0;
        act_source_r         = DTCE_RSPI0_SPRI0;
        r_dtc_set_send(&p_data_cfg_w, demo_data_source, DEMO_DATA_SIZE, &reg_buff);
        r_dtc_set_recv(&p_data_cfg_r, demo_data_dest,DEMO_DATA_SIZE, &reg_buff);
        chain_transfer_nr   = 0;

        ret_dtc = R_DTC_Create(act_source_w,
                               (dtc_transfer_data_t *)&transfer_data[0],
                               (dtc_transfer_data_cfg_t *)&p_data_cfg_w,
                               chain_transfer_nr);
        if (DTC_SUCCESS != ret_dtc)
        {
            tst_trap();
        }

        ret_dtc = R_DTC_Create(act_source_r,
                               (dtc_transfer_data_t *)&receive_data[0],
                               (dtc_transfer_data_cfg_t *)&p_data_cfg_r,
                               chain_transfer_nr);
        if (DTC_SUCCESS != ret_dtc)
        {
            tst_trap();
        }

        p_args_w.chain_transfer_nr = 0;
        p_args_r.chain_transfer_nr = 0;
        p_args_w.act_src           = DTCE_RSPI0_SPTI0;
        p_args_r.act_src           = DTCE_RSPI0_SPRI0;

        ret_dtc = R_DTC_Control(DTC_CMD_ACT_SRC_ENABLE, NULL, (void *)&p_args_w);
        if (DTC_SUCCESS != ret_dtc)
        {
            tst_trap();
        }

        ret_dtc = R_DTC_Control(DTC_CMD_ACT_SRC_ENABLE, NULL, (void *)&p_args_r);
        if (DTC_SUCCESS != ret_dtc)
        {
            tst_trap();
        }

        ret_dtc = R_DTC_Control(DTC_CMD_DTC_START, NULL, NULL);
        if (DTC_SUCCESS != ret_dtc)
        {
            tst_trap();
        }

#endif

        /* Start Slave transmit using the API function. */
        my_rspi_err = R_RSPI_Write(my_rspi_handle,
                                   my_rspi_command,
                                   demo_data_dest,
                                   (DEMO_DATA_SIZE));

        if (RSPI_SUCCESS != my_rspi_err) // Check for successful function return.
        {
            tst_trap(); // Your error handling code would go here.
        }

        /* The R_RSPI_Write() function starts the transfer and returns immediately.
         * Your callback function will be caled when the transfer is complete. We are using
         * the callback function here to update the transfer status flag. */
        while (transfer_busy)
        {
            R_BSP_NOP(); // Application could do something useful here while waiting for transfer to complete.
        }

        /* The callback retrieved the operation event result code. */
        if (RSPI_EVT_TRANSFER_COMPLETE != demo_callback_event)
        {
            tst_trap(); // Something unexpected happened.
        }

#if RSPI_DMAC_TEST == (1)
        /* === DMAC Disable === */
        ret_dmaca = R_DMACA_Control(DMACA_CH0, DMACA_CMD_DISABLE, (void *)&p_stat_dmaca);
        if (DMACA_SUCCESS != ret_dmaca)
        {
            tst_trap();
        }
        ret_dmaca = R_DMACA_Control(DMACA_CH1, DMACA_CMD_DISABLE, (void *)&p_stat_dmaca_r);
        if (DMACA_SUCCESS != ret_dmaca)
        {
            tst_trap();
        }
        ret_dmaca = R_DMACA_Close(DMACA_CH0);
        if (DMACA_SUCCESS < ret_dmaca)
        {
            tst_trap();
        }
        ret_dmaca = R_DMACA_Close(DMACA_CH1);
        if (DMACA_SUCCESS < ret_dmaca)
        {
            tst_trap();
        }
#endif

#if RSPI_DTC_TEST == (1)
        /* === DTC Disable === */
        p_args_w.act_src           = DTCE_RSPI0_SPTI0;
        p_args_r.act_src           = DTCE_RSPI0_SPRI0;

        p_args_w.chain_transfer_nr = 0;
        ret_dtc = R_DTC_Control(DTC_CMD_DTC_STOP, NULL, NULL);
        if (DTC_SUCCESS != ret_dtc)
        {
            tst_trap();
        }

        ret_dtc = R_DTC_Control(DTC_CMD_ACT_SRC_DISABLE, NULL, (void *)&p_args_w);
        if (DTC_SUCCESS != ret_dtc)
        {
            tst_trap();
        }

        ret_dtc = R_DTC_Control(DTC_CMD_ACT_SRC_DISABLE, NULL, (void *)&p_args_r);
        if (DTC_SUCCESS != ret_dtc)
        {
            tst_trap();
        }
        ret_dtc = R_DTC_Close();
        if (DTC_SUCCESS != ret_dtc)
        {
            tst_trap();
        }
#endif

        printf("loop_count = %d: ", loop_count);
        /* Check that contents of read destination buffer match the transmit buffer. */
        if (false != verify_data(demo_data_source, demo_data_dest, DEMO_DATA_SIZE))
        {
            printf("Success!\n"); // View stdout in the Renesas Virtual Debug Console window.
        }
        else
        {
            printf("Failed.\n"); // View stdout in the Renesas Virtual Debug Console window.
        }
        loop_count++;
        init_demo_data(); // Initialize demo data buffers.
    }
    /* Done using the RSPI. We can shut it down now if desired to save power. */
    R_RSPI_Close(my_rspi_handle);

#if RSPI_CFG_USE_GPIO_SSL == (1)
    poll_port(PORT_HIGH);
#endif
    /* Demo complete. Stay here. */
    while(1)
    {
        /* Do Nothing*/
    }

}
/* End of function main. */

/**********************************************************************************************************************
* Function Name: rspi_rx231_init_ports
* Description  : This function initializes the port pins associated with RSPI channel 0 for the RSKRX231 using
*                the macros defined in iodefine.h.
* Arguments    : None
* Return Value : None
**********************************************************************************************************************/
static void rspi_rx231_init_ports(void)
{
    /* Make the RSPI peripheral signal assignment selections in the MPC registers. */
    /* Set RSPI signal ports to peripheral mode. */
    R_RSPI_PinSet_RSPI0();

#if RSPI_CFG_USE_GPIO_SSL == (1) // SPI 3-wire mode.
    /* Using GPIO to control the slave select signal (Synchronous 3-wire mode). */
    PORTA.PDR.BIT.B4  = 0; // Set as output.
    PORTA.PMR.BIT.B4  = 0; // Set as GPIO.
#endif

    return;
}
/* End of function rspi_rx231_init_ports. */


/**********************************************************************************************************************
* Function Name : verify_data
* Description   : Compares contents of destination buffer against source buffer.
* Arguments     : p_data_source - pointer to transmitted data buffer.
*                 p_data_dest   - pointer to received data buffer.
*                 length        - Number of bytes to check.
* Return value  : true  - data is verified
*                 false - data mismatch.
**********************************************************************************************************************/
static bool verify_data(SPI_DATA_TYPE * p_data_source, SPI_DATA_TYPE * p_data_dest, uint16_t length)
{
    uint16_t i;

    for (i = 0; i < length; i++)
    {
        if(p_data_source[i] != p_data_dest[i])
        {
            return false;
        }
    }

    return true;
}
/* End of function verify_data. */

/**********************************************************************************************************************
* Function Name : init_demo_data
* Description   : Put some varying data in source buffer to be transmitted and clear the destination buffer.
* Arguments     : None
* Return value  : None
**********************************************************************************************************************/
static void init_demo_data(void)
{
	SPI_DATA_TYPE i;
    for (i = 0; i < DEMO_DATA_SIZE; i++)
    {
    	// todo jc: test woth 0xaa with the buspirate [0xaa:256]
        demo_data_source[i] = (SPI_DATA_TYPE)(i);  // Provide some sample data for transmission.
//        demo_data_source[i] = (uint8_t)(0xaa);  // Provide some sample data for transmission.
        demo_data_dest[i] = 0;               // Clear the receive data buffer.
    }
}
/* End of function init_demo_data. */

/**********************************************************************************************************************
* Function Name: my_rspi_callback
* Description  : This is an example of an RSPI callback function.
* Arguments    : p_data - pointer to RSPI event code data.
* Return Value : None
**********************************************************************************************************************/
static void my_rspi_callback(void *p_data)
{
    demo_callback_event = (*(rspi_callback_data_t *)p_data).event_code;
    transfer_busy = false;
}
/* End of function my_rspi_callback. */

/**********************************************************************************************************************
* Function Name: poll_port
* Description  : This function is used to wait for the input level to be equal to the expected value.
* Arguments    : level - Expected level value.
* Return Value : None
**********************************************************************************************************************/
#if RSPI_CFG_USE_GPIO_SSL == (1)
void poll_port(uint8_t level)
{
    if (PORT_LOW == level)
    {
        while(RSPI_CFG_SS_GPIO_PIDR);  // wait H->L
    }
    else
    {
        while(!RSPI_CFG_SS_GPIO_PIDR); // wait L->H
    }
}
/* End of function poll_port. */
#endif

    PI Pico source

    /**
 * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

// Example of writing via DMA to the SPI interface and similarly reading it back via a loopback.

#include <stdio.h>
#include <stdlib.h>
#include "pico/stdlib.h"
#include "pico/binary_info.h"
#include "hardware/spi.h"
#include "hardware/dma.h"

// #define TEST_SIZE 1024
#define TEST_SIZE 32

int main() {
    // Enable UART so we can print status output
    stdio_init_all();
#if !defined(spi_default) || !defined(PICO_DEFAULT_SPI_SCK_PIN) || !defined(PICO_DEFAULT_SPI_TX_PIN) || !defined(PICO_DEFAULT_SPI_RX_PIN) || !defined(PICO_DEFAULT_SPI_CSN_PIN)
#warning spi/spi_dma example requires a board with SPI pins
    puts("Default SPI pins were not defined");
#else

    printf("SPI DMA example\n");

    // Enable SPI at 1 MHz and connect to GPIOs
    spi_init(spi_default, 1000 * 1000);
    gpio_set_function(PICO_DEFAULT_SPI_RX_PIN, GPIO_FUNC_SPI);
    gpio_init(PICO_DEFAULT_SPI_CSN_PIN);
    gpio_set_function(PICO_DEFAULT_SPI_SCK_PIN, GPIO_FUNC_SPI);
    gpio_set_function(PICO_DEFAULT_SPI_TX_PIN, GPIO_FUNC_SPI);
    // Make the SPI pins available to picotool
    bi_decl(bi_3pins_with_func(PICO_DEFAULT_SPI_RX_PIN, PICO_DEFAULT_SPI_TX_PIN, PICO_DEFAULT_SPI_SCK_PIN, GPIO_FUNC_SPI));
    // Make the CS pin available to picotool
    bi_decl(bi_1pin_with_name(PICO_DEFAULT_SPI_CSN_PIN, "SPI CS"));

    // Grab some unused dma channels
    const uint dma_tx = dma_claim_unused_channel(true);
    const uint dma_rx = dma_claim_unused_channel(true);

    // Force loopback for testing (I don't have an SPI device handy)
//    hw_set_bits(&spi_get_hw(spi_default)->cr1, SPI_SSPCR1_LBM_BITS);

    static uint8_t txbuf[TEST_SIZE];
    static uint8_t rxbuf[TEST_SIZE];
    for (uint i = 0; i < TEST_SIZE; ++i) {
//        txbuf[i] = rand();
        txbuf[i] = i;
    }

    // We set the outbound DMA to transfer from a memory buffer to the SPI transmit FIFO paced by the SPI TX FIFO DREQ
    // The default is for the read address to increment every element (in this case 1 byte = DMA_SIZE_8)
    // and for the write address to remain unchanged.

    printf("Configure TX DMA\n");
    dma_channel_config c = dma_channel_get_default_config(dma_tx);
    channel_config_set_transfer_data_size(&c, DMA_SIZE_8);
    channel_config_set_dreq(&c, spi_get_dreq(spi_default, true));
    dma_channel_configure(dma_tx, &c,
                          &spi_get_hw(spi_default)->dr, // write address
                          txbuf, // read address
                          TEST_SIZE, // element count (each element is of size transfer_data_size)
                          false); // don't start yet

    printf("Configure RX DMA\n");

    // We set the inbound DMA to transfer from the SPI receive FIFO to a memory buffer paced by the SPI RX FIFO DREQ
    // We configure the read address to remain unchanged for each element, but the write
    // address to increment (so data is written throughout the buffer)
    c = dma_channel_get_default_config(dma_rx);
    channel_config_set_transfer_data_size(&c, DMA_SIZE_8);
    channel_config_set_dreq(&c, spi_get_dreq(spi_default, false));
    channel_config_set_read_increment(&c, false);
    channel_config_set_write_increment(&c, true);
    dma_channel_configure(dma_rx, &c,
                          rxbuf, // write address
                          &spi_get_hw(spi_default)->dr, // read address
                          TEST_SIZE, // element count (each element is of size transfer_data_size)
                          false); // don't start yet


    printf("Starting DMAs...\n");
    // start them exactly simultaneously to avoid races (in extreme cases the FIFO could overflow)
    dma_start_channel_mask((1u << dma_tx) | (1u << dma_rx));
    printf("Wait for RX complete...\n");
    dma_channel_wait_for_finish_blocking(dma_rx);
    if (dma_channel_is_busy(dma_tx)) {
        panic("RX completed before TX");
    }

    printf("Done. Checking...");
    for (uint i = 0; i < TEST_SIZE; ++i) {
        if (rxbuf[i] != txbuf[i]) {
            panic("Mismatch at %d/%d: expected %02x, got %02x",
                  i, TEST_SIZE, txbuf[i], rxbuf[i]
            );
        }
    }

    printf("All good\n");
    dma_channel_unclaim(dma_tx);
    dma_channel_unclaim(dma_rx);
    return 0;
#endif
}

  • in reply to Jan Cumps

    correction: it isn't a difference in toolchain. I redid my project with CC-RX compiler, and I have the same behaviour.

    It's a difference between how my code and config behaves, vs the original example...

  • Warning to me 2:

    SPI behaviour with Rensas toolchain and GCC is different.

    For the same set of test data, generated under identical conditions by a Bus Pirate,
    the Renesas version hops happily along, while the GCC version returns a buffer underflow after a few 256 bytes exchanges....

  • Warning to me:

    • if you use the RX as slave, and the SPI master is a different device powered from a different source
    • and both devices are on
    • and then you power down the RX,

    it says powered on via the CS, as long as that pin is being being pulled high by the master.

    Proper power sequencing seems to be needed.