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  • Author Author: Eavesdropper
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Self-repairing processor

Eavesdropper
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CRISP has developed a multi-core processor that will test and repair itself, sort of. There is an on-board resource manager that will test to see if a core is malfunctioning, and if so, send the tasks to a functioning core. The idea is to create a chip that will always work 100% of the time regardless of internal component failures. ‘‘Because of the rapidly growing transistor density on chips, it has become a real challenge to ensure high system dependability. The solution is not to make non-degradable chips, it's to make architectures that can degrade while they keep functioning, which we call graceful degradation. With the right dependability infrastructure many-cores can be a solution', says Hans Kerkhoff accociate professor at the University of Twente.

 
Still in the design, prototype, stage, this technology may very well be the standard future of chip design. My old critic is what is the "resource manager" gets corrupted due to a bad core? I'm sure more details will emerge over time on how they will handle such events.

 
CRISP stands for Cutting edge Reconfigurable ICs for Stream Processing. It is a collaborative effort from the University of Twente, Tampere University of Technology, Thales Netherlands, Recore Systems, Atmel, and NXP at the moment.

 
Eavesdropper
  • in reply to Former Member

    Regule,

    You are correct. I think they wanted to say self-repairing because it would make people read about their development. Still, it is a great concept. Compared to a standard processor, it stay up and running. This would save so many of my computers and gadgets. And I am sure satellites being able to stay up and running without intervention is a big reason for the work.

     

    E

  • I think that fault-tolerant  better describes this solution then self-repairing , because from what I understand

    it cannot repair corrupted parts only reallocate tasks from them to other cores.

  • There was a lot of work done on this subject by TRW during the 1990's for integrated avionics.  They approached the problem by using one processor to come up as the master, but each processor in turn would have a timed delay to see if the a master had asserted control.  If not, then the next processor that timed out would assume master control and allocate the processors to tasks as needed.  Based on the block diagram, a similar approach would probably work here.

    Thanks,

    DAB