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Cyclone II Max Clock Rate

bluesea

I am trying to get the most from my chip (EP2C20F484C7N). I have tried searching but everywhere seems to say different with no real reason to why that is the max rate.

In the datasheet from what I can see the max clock is 260Mhz.

However, I have found information to hint that it can go higher than this. For example, using both the rising and falling edge of the clock, PLL etc..

Can anyone share information on this?image

Parents

  • The max clking of an fpga is dependant on several things e.g. the fpga itself(including flipflop technology, routing...and other electrical level stuff that belongs to silicon people.) as well as the field engineers skill, design density speed density and the design itself(dedicated blocks usage and so on).
    It also may vary with different sections of same fpga.

    It is therefore hard for vendors to state exact figures but they only give an idea and in a comparative approach.

    The notion of using both edges is a trick to overcome clk speed limitation, usefull on board. You pass data at double clk speed onto two sets of registers but inside fpga ultimately a double clk is needed(clking one set of registers) to process data in their order.

    Your question on PLL: this is a different issue, you may generate fast clk but you need fpga to support that speed.

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  • The max clking of an fpga is dependant on several things e.g. the fpga itself(including flipflop technology, routing...and other electrical level stuff that belongs to silicon people.) as well as the field engineers skill, design density speed density and the design itself(dedicated blocks usage and so on).
    It also may vary with different sections of same fpga.

    It is therefore hard for vendors to state exact figures but they only give an idea and in a comparative approach.

    The notion of using both edges is a trick to overcome clk speed limitation, usefull on board. You pass data at double clk speed onto two sets of registers but inside fpga ultimately a double clk is needed(clking one set of registers) to process data in their order.

    Your question on PLL: this is a different issue, you may generate fast clk but you need fpga to support that speed.

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