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High Speed Asynchronous Counter Design?

Former Member

Does anyone have any sugestions as to what hardware I should use for a 100MHz + asynchronous counter design. The pulses will be about 1ns wide so may need broadening and could occur with a 2ns interval occasionally (yes I know that is 500MHz but this is for stats so missing the odd pulse is not critical).

 

Even at 100MHz we are beyond CMOS so do I need to look at CPLD's or do I need to go up to a fast FPGA?

Any other ideas?

 

Thanks

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    I would think that FPGA would be the way to go (though if this is all you are doing then it way be considered by some to be a 'waste' of the rest of the resource on a high-end fpga!

    I expect a CPLD may cope at the lower-end but towards the higher end (500Mhz) it would probably struggle, though you may be able to find a more capable high end one. I recommend you have a look at what is available on the market - I expect your primary consideration would be the 'speed-grade' of the devices (though be warned this has a DIFFERENT meaning for FPGAs than it does for CPLD devices.

     

    I hope this helps

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    I would think that FPGA would be the way to go (though if this is all you are doing then it way be considered by some to be a 'waste' of the rest of the resource on a high-end fpga!

    I expect a CPLD may cope at the lower-end but towards the higher end (500Mhz) it would probably struggle, though you may be able to find a more capable high end one. I recommend you have a look at what is available on the market - I expect your primary consideration would be the 'speed-grade' of the devices (though be warned this has a DIFFERENT meaning for FPGAs than it does for CPLD devices.

     

    I hope this helps

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