Interfacing MCUs to external SDRAM

Hello Marco,

an external memory interface is always interesting and can involve a lot of issues.

Usually the supplier of your controller chip will have Design Guides how to implement the memory interface.

Of course you should take a look at the Spec of your DRAMs (JEDEC and from manufacturer).

And I also might be able to answer your questions, but they need to be more specific and I need some more information (wchich MCU, how many DRAMs, which DRAM generation, which DRAM organization, Stackup of your board and minimum feature size you intend to use, .. )

Best regards

Hermann

Hi Marco,

To access external memory, you need to configure a way to address the memory and read or write data over its buss width.  Go look at the old Z80 or 8085 cookbooks, they will show you the basic architecture of how to set up a memory bank.  If you really dig, you can find the software design used to set up the memory as a storage medium called a ram disk.  We used to make these all the time to get over the old floppy disk or casette tape delay times.

The interface can be simple or complex, it depends upon the MCU you have, how many digital pins you have free, and how wide of a data bus you want.  After that, the configuration of the logic circuit is fairly simple.  One caveat, dynamic ram requires a refresh circuit or controller which can get pretty involved.  So I would go to static ram if you have a choice.

Good luck,

DAB

Hey Marco

I don't know the specifics of what you doing but a typical approach if your looking for parallel RAM (you can get serial SRAM if access speed isn't a concern) is to select a SRAM, the important parameters being voltage obviously, and then bus width (8/16/32) and access speed.  Then typically you use something like 74HC573 IC's to latch the address from your data bus to the SRAM address pins, using multiple 74HC573's if your bus is bigger than 8 bits.  If you want as fast as possible speed select a MCU with a built in parallel port so the MCU accesses the ram as fast as possible rather than you bit bashing the accesses, but if you don't need get the speed as fast as possible then there's nothing wrong with bit bashing the accesses and your typcailly only talking about a few extra MCU cycles per access.

Hello Hermann, DAB and Adam,

Thank you for your fast answers.

I give some more info.

The MCU I use in this project is the Renesas SH7216 and, from the requisites, I should interface 8MB Parallel Flash + 8MB SDRAM to the MCU (SH7216 has a built-in refresh controller).

Now, I think that the use of SRAM (static) instead of SDRAM is not the best choice because looking around RAM providers I've seen that 8MB is a pretty big capacity for a SRAM type and also the costs rise up considerably.

The Bus size is 16 bit. the SDRAM could be the Samsung K4S281632K-UCL60, for the FLASH I'm still looking around for a very fast one (suggestions?).

I'm thinking to develope the board layout on a 4-layers PCB. I know that termination/debounching resistors for the MCU-SDRAM data/address interface also depends on the PCB layout but I wish to understand if there are "good design rules" for this kind of interface. The MCU datasheet don't say much about layout and terminations for SDRAM interface. For example, why in some schematics addresses termination resistors are 0 ohm?

Regards.

Marco.

Hi Marco,

modern MCUs with SDRAM controller are very easy to interface to SDRAM. Just connect the pins, with small series resistors (10Ohm is quite common) to control rise times and dump reflections if needed.

Clock trace should follow specific rules depending on the path lenght (if the distance between MCU and SDRAM is less than 1" you don't need to).

On my experience, problems arise when you need to program the controller with the correct set of timing parameters for the SDRAM. Be careful and use only well documented chips.

regards

Hi Luca,

This is the answer I was looking for. Thank you.

I've seen in some datasheets that the series resistors connected to the data bus have different value from those connected to the address bus. I think this is due to the different parameters value (capacitance ?) between SDRAM data pins and address pins. So what parameters are kept into account to choice resistors values? Is there is a formulae I can use to calculate (approximately) the value of these resistors?

Best Regards.

Marco.

If the track is short you can simply check the cutoff frequency of an RC filter made by

R = Rdriver + Radded, Rdriver typical 20 Ohm

C = Cpin + Cstray, Cstray typical 3pF

Frequency shall be higher than 5*Fbus.

With long traces, microstrip effects complicate the problem so this becomes a task for an SI tool.

regards

Hello,

the use of the serial termination and the corresponding value depends on your system configuration.

If you have more DRAMs usually all DRAMs are connected to the CA bus, while on the Databus it depends how many ranks you are going to implement.

As Luca said in addition it depends also on the trace length of your signals.

If your DRAMs use ODT you do not need any serial termination on the Databus at all.

The main issue i have seen are overshoots if the serial resistance is too small. Most people do not care, but I have seen several fails due to overshoots in the past (of course because I usually do only get failing desings for debugging, so I don't see all the working designs ;-)   ).

The value of serial termination also depends on the flexibility of your Controller (and the used DRAMs) on Drive strengh setting. Some Controllers and  DRAMS do have several drive strength settings.

So without knowing your system configuration it is difficult to give a number.

Assuming a single DRAM DDR2 DRAM not utilizing ODT and traces in the range of 5-7cm I would use 22 Ohm as inital guess for all DQ and CA lines using half drive strengh on the DRAM and any kind of low drive strengh on the controller. Clock terminated differential at the DRAM.

But as mentioned: this all depends on the configuration that you are going to use.

There are two options to get this done:

- place the resistor and measure signal integrity and adjust your BOM accordingly (of course requires a scope with corresponding bandwith).

- Simulate the design (maybe even with a free spice).

If you use any kind of upper speedgrade DDR2 or DDR3 you should consider the normal high speed routing guidelines...

best regards

Hermann

EDIT: Sorry, I have not seen that you posted your system configuration above.. somehow I did not see the e-mail notification on this post .. I will check this one, but I guess Luca's answer does consider this already ...

I just checked the DRAM component:

Its an SDR Component running at 83MHZ ("PC166").

So forget on my comment on differential termination of the clock at the DRAM    ;-)

Even below 100MHz I would some "high speed rules" for such a design:

- use impdeance controlled routing (around 60 Ohm),

- not crossing any slot in reference

- Physicaly seperate the different busses: CCA (Controll, Command, Address) vs. DQ bus (in order to avoid uncorrelated X-talk).

With a single x16 component you should be able to stay below 6-7cm routing length. So the proposal of 22 OHm termination in all lines might match the configuration quite well.

It's quite a while ago I used SDR components, but I would assume they had a reduced drive strength already, so the question is if the MCU also support a reduced drive strength (or maybe only have a reduced drive strength   ;-)   )

But in any case verifying the Signal quality on a prototype is strongly recommended ...

I expect that this MCU does not support any more actual kind of DRAM ?!?. The SDR components will be more and more difficult to get and so the question is if it makes sense to start a new design with this technology...

Hermann

Hi Luca,  Hi Hermann,

Thanks to your support I'm giving expertise more and more.

You have centered the matter.

I see that, in general,  this kind of circutry can not be made pefect at design time only. It's necesary find the best "balance" also during test time to have signal integrity.

The main rules I understood are (correct me if I do wrong):

At Schematic Design time place 22Ohm series resistors in all signals of all control, address and data buses, even if the related PCB tracks are short (eg. less than 1").

At PCB Routing time place the series resistors close to the SDRAM side.

At PCB Routing time place bus tracks to have 50Ohm of impedance (is this necessary only for long traces (>2") or also for short traces?)

At PCB Routing time, for each bus, design tracks to have the same path, lenght, width and layer. Better with no vias. If the track width is X then the distance between tracks must be 3X minimum (to avoid crosstalk).

At test time verify the signals integrity with a proper SDRAM access firmware and oscilloscope. Tune resistors values if necessary.

I've seen some solutions having series resistors in both MPU and SDRAM size in the same bus signals. Is it required for very long bus traces?

Drive strength is a new for me. I do have a look what the MCU datasheet says.

Hermann,

You all right, there are better MPU choices to accomplish external SDRAM interface, but my requirements are 1-2MBytes internal flash (programs must run on internal flash for safety), intergrated ethernet, interrupts channel, etc. and at the moment this MPU is the solution for me. All because this project is a communication gateway for embedded systems, at automotive grade.

I coming from 8bits sigle chip MPU projects, with all flash and RAM intergrated. This new project is pretty a big jump for me.

Thank you and Best Regards.

Marco Grechi.