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Embedded Forum Get Your Xilinx FPGA/Programmable SoC Questions Answered here
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Related

Get Your Xilinx FPGA/Programmable SoC Questions Answered here

rscasny
rscasny over 6 years ago

In the past year or so, the element14 community has been offering quite a few programs, contests, and initatives around Xilinx's FPGA and heterogeneous SoC, ZYNQ. We have hosted webinars, run roadtests, and offered a training program last year called Path to Programmable.

 

I see element14 member interest in Xilinx product knowledge on the rise. I plan on offering more Xilinx-related projects and roadtests in the coming months. (Stay tuned to Path to Programmable 2 with the Ultra96v2) Given all this activity, I thought it would be a great idea to bring in a Xilinx product expert for some well needed Q&A time. So let me introduce you to Adam Taylor ( adamtaylorcengfiet ).

 

I believe Adam has been an element14 member for several years. He is the Director of ADIUVO Engineering. He is a Chartered Engineer and Fellow of the Institute of Engineering and Technology. He is well known for his Microzed Chronicles. He writes the Exploring the Programmable World for element14. Adam has been instrumental in developing element14's FPGA/Programmable SoC Essentials.

 

Adam also is an expert in the PYNQ framework: Python for ZYNQ productivity. So, if you are asoftware developer who wants to explore the Programmable world, I'd encourage you to ask Adam your top questions.

 

So, if you have any questions revolving around FPGAs, programmable SoCs, a project in progress, perhaps even a question about Vivado, please click REPLY and asked them here.

 

Sincerely,

 

Randall Scasny

-element14 Team

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Top Replies

  • jomoenginer
    jomoenginer over 6 years ago +4
    Awesome! It's great that adamtaylorcengfiet is a resource on element14 for Programmable SoC questions. I'm sure I will have many as I finish my Digilent Zybo Z7 RoadTest. I do find Adam's Microzed Chronicles…
  • jomoenginer
    jomoenginer over 6 years ago +4
    For what it's worth, there is an Integrating Arm Cortex-M soft CPU IP into FPGAs virtual workshop that features Adam Taylor as an instructor and uses the Digilent Arty S7-50T to be held August 14th, 2019…
  • wolfgangfriedrich
    wolfgangfriedrich over 6 years ago +3
    I would appreciate any comments on a process on how to make the DDR3 SDRAM MIG work without using the AXI interface in VHDL. As a target platform I have the Digilent Arty S7 board. I tried this during…
  • adamtaylorcengfiet
    adamtaylorcengfiet over 5 years ago in reply to grainne1397

    There is a XADC available, though I am not sure what the pins are mapped to externally you would have to check the schematics.

     

    You can access the XADC using the IIC drivers check by blog here

     

    https://blog.hackster.io/microzed-chronicles-petalinux-and-xadc-9ae052539d1f

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  • ralphjy
    ralphjy over 5 years ago

    This question is for adamtaylorcengfiet  -

     

    I'm one of the trainees in the Path II Programmable course.  I'm encountering an issue that hopefully you've seen before.  At the end of HW Lab7 when I am trying to write the bitstream for the design with new IP added, synthesis runs successfully but implementation fails during optimization.

     

    Here is an excerpt from the impl/runme.log:

     

    Starting Logic Optimization Task

     

    Phase 1 Generate And Synthesize Debug Cores

    INFO: [Chipscope 16-329] Generating Script for core instance : dbg_hub

    INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:xsdbm:3.0 for cell dbg_hub_CV.

    ERROR: [IP_Flow 19-3805] Failed to generate and synthesize debug IPs.

    ERROR: [Common 17-161] Invalid option value '0' specified for '-jobs'.

    ERROR: [Chipscope 16-330] Synthesis of Debug Cores has failed

    Phase 1 Generate And Synthesize Debug Cores | Checksum: 24bc6163a

     

    Time (s): cpu = 00:01:01 ; elapsed = 00:03:50 . Memory (MB): peak = 2532.340 ; gain = 1.000 ; free physical = 1191 ; free virtual = 3762

    INFO: [Common 17-83] Releasing license: Implementation

    17 Infos, 0 Warnings, 0 Critical Warnings and 3 Errors encountered.

    opt_design failed

    ERROR: [Chipscope 16-338] Implementing debug Cores failed due to earlier errors

    INFO: [Common 17-206] Exiting Vivado at Tue Oct 22 20:02:55 2019...

     

    I can send you the full synth and impl logs if that will help.  I saw on the Xilinx forum that this could be related to the version of Ubuntu installed.  I wanted to check with you before I go through trying to install another version.  Here is the link to the forum https://forums.xilinx.com/t5/Implementation/Invalid-option-value-0-specified-for-jobs/td-p/881190

     

    I am running Ubuntu 16.04.6 in the VM.

     

    I also tried running the tcl command "check_ip_cache -clear_output_repo"

     

     

     

     

    Thanks,

     

    Ralph

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  • dimiterk
    dimiterk over 5 years ago

    Hello,

     

    I have a question with regards to the project Adam has posted under here:

    https://www.hackster.io/adam-taylor/creating-an-fpga-based-low-cost-imaging-system-cb18af#comments

     

     

    Rgearding the quote below:

    As we have no VDMA it is important the video output on the AXIS stream is a contiguus block and that TValid does not assert and deassert during the active pixel period.

     

    Can you use a AXIS clock crossing block instead of the FIFO or is that needed to avoid TVALID deserting periodically during the active pixel period?

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  • adamtaylorcengfiet
    adamtaylorcengfiet over 5 years ago in reply to ralphjy

    Hi Ralph

     

    2018.3 I assume you are using that tool chain,  does not support that version of Ubuntu it supports 16.04.03 or 16.04.04 which might be the cause of the issue

     

    Adam 

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  • adamtaylorcengfiet
    adamtaylorcengfiet over 5 years ago in reply to dimiterk

    No the FIFO is to buffer a pixel line so we do not get blank spots in the display when we are outputting the video

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  • dimiterk
    dimiterk over 5 years ago in reply to adamtaylorcengfiet

    How do you deal with a scenario where the camera is operating on a different domain clock?

    Wouldn't there be back-pressure (TVALID toggling) from the AXIS to Video out.

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  • ralphjy
    ralphjy over 5 years ago in reply to adamtaylorcengfiet

    Hi Adam,

     

    Thanks.  I had explicitly not upgraded to Ubuntu 18.04 and Xilinx 2019.1 because I did not want to have compatibility issues with the course.  Is it better to upgrade now or should I try to revert back to 16.04.03?

     

    Interestingly, I had continued to the next lab using the HDF solution that you provided and I did not have this issue generating the bitstream for the final lab.  I guess my main concern is that I don't run into problems when I move on to my project after I finish the course.  What specific tool flow would you recommend?

     

    Ralph

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  • adamtaylorcengfiet
    adamtaylorcengfiet over 5 years ago in reply to ralphjy

    The course I think is designed around 2018.3 so you should use that tool chain and make sure the VM aligns with it. That way you should be able to follow along with the labs nice and easily and not hit any issues re IP versions etc.

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  • dcsoutherner
    dcsoutherner over 5 years ago

    The SDK (2019.1) under Ubuntu 18.04.3 will not complete loading, but halts silently when loading eclipse components.  The host uses an INtel Core I7-3770 CPU with 16 GB or memory and has plenty of memory and disk available when I invoke the SDK from Vivado.

    How can I find out what is causing the halt?

    Thanks

    Cliff

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  • adamtaylorcengfiet
    adamtaylorcengfiet over 5 years ago in reply to dcsoutherner

    You could take a look in the SDK log, I think it will be the project directory <project>.sdk

     

    However, the version of Linux your using does not look to supported in 2019.1 https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug973-vivado-release-notes-install-license.pdf  states 18.04.01

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