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PIC10F microcontroller output pin tolerance to overriding voltages

davebullockmbe

I am using PIC10F microcontrollers in a wireless project that has evolved into needing to use an 'in circuit' programmable radio IC.

The problem is that the GP2 pin of the PIC would be connected to the DATA input (and programming) pin3 of the radio IC.
The whole circuit is running off 3v7 lipo battery.
My question is will the PIC GP2 output be destroyed when programming the radio IC. ?

Thanks in anticipation....

Daveimage

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  • 0

    If you could hold the processor in reset, GP2 would be tri-stated...

  • 0 in reply to scottiebabe

    Yes the problem with adding a diode in series with the data line is as you say the data pin of the radio chip will float and so need a resistor to pull it down. Unlike Microchip datasheets I cannot find any information about the internal structure of these radio IC's ie. whether they have internal pull-ups/downs. I have just about run out of board space and am struggling to add even one more component.
    However putting the PIC10F202 into reset would be a great idea but doesn't this need extra PIC code to force the o/p pins into tristate. I don't think toggling MCLR does this on it's own?
    Dave

  • 0 in reply to davebullockmbe

    You can set GP2 as an input to prevent it from loading the radio pin during programming:

    From the Microchip data sheet.

    5.2 TRIS Registers
    The Output Driver Control register is loaded with the
    contents of the W register by executing the TRIS f
    instruction. A ‘1’ from a TRIS register bit puts the corresponding
    output driver in a High-impedance mode. A
    ‘0’ puts the contents of the output data latch on the
    selected pins, enabling the output buffer. The exceptions
    are GP3, which is input only and the GP2/T0CKI/
    COUT/FOSC4 pin, which may be controlled by various
    registers. See Table 5-1

    MK

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  • 0 in reply to davebullockmbe

    You can set GP2 as an input to prevent it from loading the radio pin during programming:

    From the Microchip data sheet.

    5.2 TRIS Registers
    The Output Driver Control register is loaded with the
    contents of the W register by executing the TRIS f
    instruction. A ‘1’ from a TRIS register bit puts the corresponding
    output driver in a High-impedance mode. A
    ‘0’ puts the contents of the output data latch on the
    selected pins, enabling the output buffer. The exceptions
    are GP3, which is input only and the GP2/T0CKI/
    COUT/FOSC4 pin, which may be controlled by various
    registers. See Table 5-1

    MK

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