Who wants to have FPGA fun for free?

I would loose 100 pounds (over 10 months or less) to have this Papilio board.  I am currently reading an entire college text book about VHDL and FPGA programming. 

I would loose 100 pounds (over 10 months or less) to have this Papilio board.  I am currently reading an entire college text book about VHDL and FPGA programming. 

Drew

B***g the random selection, lets see the before and after photos of Billabott as he heads out on this double challenge.

Another strange header arrangement, but at least its 0.1 spacing.

Mark

I will not be held responsible for any physical defect (vision loss) incurred or mental damage suffered by looking at my before and after photos.  That said, I can deal with that request.  Thanks for the supportive voices, guys!

billabott wrote:

I am currently reading an entire college text book about VHDL and FPGA programming. 

Peter Wishart wrote:

I have been learning VHDL for the last month but I don't have a FPGA board yet to try the exercises in the book, this board would help me a lot.

Unless you really enjoy typing, you might check out Verilog.  Verilog is based on C, so it has less verbiage than VHDL, which is based on Ada.

Unless you really enjoy typing, you might check out Verilog.  Verilog is based on C, so it has less verbiage than VHDL, which is based on Ada.

I don't want to start a language war, but I have noticed that some novice C users

have posted examples of code in the e14 arduino forum where mistaken substitutions,

like "if" when "while" was meant, would have been detected much easier by the

compiler in a language like Ada that has some intentional redundancy in its syntax.

So I think there is a tradeoff between less verbiage for one language and better

compile-time error detection for the other.

coder27 wrote:

 

I don't want to start a language war, but I have noticed that some novice C users

have posted examples of code in the e14 arduino forum where mistaken substitutions,

like "if" when "while" was meant, would have been detected much easier by the

compiler in a language like Ada that has some intentional redundancy in its syntax.

So I think there is a tradeoff between less verbiage for one language and better

compile-time error detection for the other.

At the last Design West conference, a speaker said he preferred to have his engineers write VHDL instead of Verilog because the latter is so C-like that some engineers would think in terms of software rather than hardware and design things poorly.  My opinion is that you shouldn't stop people from using power tools just because a few people won't use them safely.

Regarding languages in general, my opinion is chacun a son goût (YMMV).  People should use languages that they're comfortable with and that express their problems in a clean, familiar way so that bugs are obvious and maintenance isn't a nightmare.

Pax vobiscum

@Peter & John

I think it might depend on where you start: I started with VHDL and am currently getting up to speed on Verilog because to is very widely used and I have to support customers using it, or bits of IP wrritten in it.

I HATE Verilog !

VHDL is based on ADA and System Verilog (no one uses just plain Verilog) is based on C and a dog's breakfast.

This comment refers to ADA  and C but is just as relevant to VHDL and Verilog:

"I would rather learn to code in VHDL than to debug in Verilog"

Of course in real life it's more complex than that but I would recommend that you start in VHDL (it forces you to think more about the underlying hardware).

MK

Michael Kellett wrote:

 

@Peter & John

 

I think it might depend on where you start: I started with VHDL and am currently getting up to speed on Verilog because to is very widely used and I have to support customers using it, or bits of IP wrritten in it.

 

I HATE Verilog !

 

VHDL is based on ADA and System Verilog (no one uses just plain Verilog) is based on C and a dog's breakfast.

 

This comment refers to ADA  and C but is just as relevant to VHDL and Verilog:

 

"I would rather learn to code in VHDL than to debug in Verilog"

 

Of course in real life it's more complex than that but I would recommend that you start in VHDL (it forces you to think more about the underlying hardware).

 

MK

IMO it depends a lot on how you write your Verilog.  I use "just plain" Verilog as a register-transfer language and avoid the behavioral constructs that get in the way of my understanding of the logic.  If you write it this way it matches the hardware quite closely.  Others prefer to use highly behavioral notations and I find that code to be practically unreadable -- the phrase "dog's breakfast" is apt.  Of course, others might say the same for my code

Perhaps Verilog -- like C -- permits more abuse than VHDL or Ada.  I don't have enough experience with the latters to form an opinion.

My favorite HDL written by other people is Altera's AHDL, which is a very clean register-transfer language.  I used it for some (IIRC) 6000-series FPGA design and it went very well.  I don't think they support it any more

There's a fundamental problem with both VHDL and Verilog: neither was created as a design language for synthesizing logic.  From what I recall, VHDL was created as a specification language for VLSI chip behavior, so it's a good language for simulation.  Similarly, Verilog was created for test pattern generation and checking, so again it emphasizes behavior and simulation.  I think there's plenty of room for a language that's better suited for describing and synthesizing hardware rather than behavior.