It's hard to win a race if you can't get off the blocks... it's hard to throw a touchdown if you can't take the snap... it's hard to... you get the point.
I've been designing power around FPGAs, specifically Xilinx for almost 20 years. Wow, that doesn't sound right when I say it out loud. Anyway, to get the most out of these parts the power system can sometimes become fairly complex. Start up of your power supplies is typically the highest stress point of operation. Think about it, when your electronics fail do they fail randomly during operation or is it more common that they die trying to power up? (Ok inadequate thermal relief during operation is the other biggest killer but that's a blog for another day). I like the light bulb analogy, it's more likely to blow up when you flip the switch than burn out once it's running.
A lot of devices have not only sequencing requirements but startup ramp requirements as well. If you are lucky then all the devices that share supplies have the same sequencing requirements. We don't always get lucky. A lot of times though even if they don't match, devices will allow you to start up simultaneously. That seems like a good solution too, just be sure you don't overlook design techniques that can greatly reduce the stress on your design.
While there is no way to eliminate the inherent strain of rapidly charging bulk capacitors and a decoupling network along with starting up silicon devices, we can try to minimize the strain by designing in proper sequencing and startup profiles of our supplies. Let's take a look at the current draw during the startup of a supply powering an FPGA:
A few things should jump out at you. During that ramp from 0 to Vcc the bulk of your current, typically called inrush current, is drawn by the bulk capacitance on the outputs of your supplies. If I want to try and control that peak current, what is the easiest way to do it? Go back to your current equation I = C (dv/dt). Increase the "t" to reduce the "I". If you can slow down the ramp of your power supplies, your peak current during startup will be reduced. Most startup requirements specify a monotonic rise, meaning no negative dips during startup. Slowing down the ramp reduces the power load which helps keep that ramp stable. It also reduces the stress on the input supply.
The input supply is an important thing to remember and also ties in the importance of sequencing. Let's say we have an AC/DC supply providing 5V to our system. That 5V is then used to power all the DC/DC regulators on the board. What happens if we throw the switch and all the DC/DC supplies on the board are pegged to fire up at the same time? All those peak inrush currents happen simultaneously, demanding a larger current spike and producing a voltage transient on that input supply. A 4A supply may be sufficient to handle your maximum expected operational current, however it may not be enough to provide the instantaneous current demand of all your supplies starting at once. As the temperature changes, that startup current is going to change as well. Maybe what works at room temperature draws more current at cold and causes an overcurrent or undervoltage shutdown (I've had that). If we take that same design and slow the ramp times we can reduce that load demand. Even better, if we can slow the ramp times while also sequencing the supplies we can lower the individual demands and provide them sequentially instead of in parallel. By doing so you greatly reduce the peak current strain on your power system without dramatic changes to your architecture.
I'm a big fan of nice slow startups. Like everything else though there are tradeoffs and you need to make sure you don't violate startup requirements or timing requirements in the process. For example, sequentially starting the supplies to the FPGA is great, but if you do it too slowly, you can violate the power on reset timing if the reset is released before the full power tree is up (I've had that too). Many devices have a range for recommended startup time. The range on many of the Xilinx supplies is 0.2ms - 50ms. If you are using programmable power supplies (Infineon PMIC updates to Avnet products ) you have the freedom to modify these startups after the hardware has been designed. That can be helpful if you throw a scope on the outputs and see dips during downstream supply startups. You can modify the startup time and see if your transients go away.
Try to start your supplies slow if you can and keep in mind that even if sequencing isn't required, as long as it doesn't violate any specs, it can still be very beneficial.