MOSFET recomendation for LTC4008 Li-ion Charger (5 cells pack)

Question

Hi,

I´m currently designing a 5 cell pack Li-ion charger with LTC4008 chip (discussion posted in Sep 2011 in this thread)

In page 15 of LTC4008 datasheet you can find the topic about the MOSFET selection.

I´m certainly lost in the proper selection. I know that logic-level MOSFETS must be used (gate voltage around (5.6V-6V), but is the first time for me designing with mosfets.

One important point is the output voltage of the carger, datasheet says that if Vout>20V then the RDSon should be little more high for reducing the ripple...

The charge voltage will be 20.5V and maximum Output Current 1.5A

I was thinking on use the mosfets that appear in the schematics of the datasheet, but has anyone any recommendation?, I mean, do I have to go deep in the mosfets area or can I use one recommended by anyone who has be involved in similar scenarios?

The only important thing in this design is the proper selection for minimum ripple current, at cost of something (as always). Efficiency for example is not a problem cause it´s a battery charger (I prefer to lost energy efficency if that means reduce ripple current in the output). I´m thinking to use a slightly high Inductor (around 40 microH) and two low ESR tantalum capacitors "surge robust" in parallel in the output of the mosfets.

Any comments are appreciated

PS: I need reference values. (What means high ... what means low... 0.001 - 0.01 ? (in mosfet parameters)

Former Member · Accepted Answer

Notes on this thread from LTC factory applications. NOt from me. There are a number of misinformed thoughts here in this thread. The issues at hand are a power supply book unto themselves. Here are my responses to the most salient points. The DS does not at all relate the ripple with the RDSon. These are fundamentally different quantities. RDSon is the effective steady-state on-state resistance of a MOSFET. Output (voltage) switching ripple in a PWM circuit is a function of the on/off states of the MOSFET pair in conjunction with the inductor. This voltage pulsing causes the current through the inductor to go up and down in a triangular manner. If this were directly applied to the output, you could have horrible results. Thus it is filtered with the output capacitor. What I believe he is referring to is actually the ESR (equivalent series resistance). This is discussed in pg. 14-15. (The value of the capacitance and voltage rating largely affects the sort of expected ESR range given a specific part family due to the physical construction of the capacitor.) Choose the capacitor appropriately in relationship to the “acceptable” amount of the voltage ripple. I am speaking comparatively here and according to what is being addressed by pg. 16. RDSon is indirectly related to is the switching (or transition) loss, which is a function of many parameters, but gets worse with higher VIN because you must use FETs with higher voltage rating. Two things happen: Increasing the voltage rating and trying to keep a similar RDSon inherently increases the gate charge (Qg) and capacitance (CSS, etc.), both contributing to higher losses. The RDSon goes up (usually) if you try to keep the same Qg relative to the previous choice at the lower voltage rating. The only the circuit designer can control is to use a FET with lower Qg and Miller capacitance figures, but therein is the trade-off to higher RDSon. For the same voltage rating of FET, you will have to compromise between lowest RDSon and lowest Qg. This is what relates to the efficiency degradation. In the case of the battery charger, we are mostly concerned with finding the happy medium of minimizing the transition losses and maximizing efficiency hit. The FETs used in the demo circuit are acceptable for use in this app, however I would caution the use of an input voltage too close to the FET rating as the switch node will see switching peaks slightly higher depending on the parasitic trace inductance due to layout. It is small and finite, but there are ways to minimize its effects. The switch node can be snubbed out with an RC circuit, but usually the best bet is to minimize the distance from the FETs to the inductor. Or even simpler & safer, use a 40VD-S rated FET. General FET selection tips: Choose your vendor. This is non-trivial if you have bizarre requirements, but in this case the trickiest component is the top FET, which is a P-channel MOSFET. Vishay and Fairchild have been our choices in the past. Choose according to the maximum voltage they will see. In the case of this design, the input and output voltage exceeds 20, so a 30V should be acceptable. However, intuitively you would know that if the input were at 29V, this would be a marginal situation and so should actually be upped to 40V rating. Judgment and experience will show best what is necessary, but a good PCB layout should not see a large excursion. As my personal rule of thumb, I like to estimate at least a ~5V differential between max rating and the max voltage applied to the circuit. As I said, the peak can actually be a little higher due to trace inductance. Next, choose what is an acceptably rated gate drive according to the switching controller in question. Most LTC parts run a 5V gate drive, which is a common rating. This limits the choices further. Choose the preferred package type. In this case, the design could be accomplished with SO-8 or smaller due to the current levels. There should be no reason to “overdesign” the circuit; it can be costly and has diminishing returns for many other reasons. Among the maybe 5-10 choices remaining from the filtering above, choose one with appropriate current rating. In a buck, the worst-case current is seen by the The customer is correct in observing most people don’t care too much of the efficiency of the circuit. Since this is a buck topology, the efficiency can be expected to be in the low- to mid-90s anyway, assuming decent component choices. As for the # of cells, there is a finite number of combinations you want to allow for in the design of a demoboard for common usage. The stacks used back during its design probably did not go past 4-cells, so to design up to 6 may have been a little difficult while still maintaining one inductor value and a simple battery voltage jumper setting. Since the voltage is actually “continuously adjustable” via resistor, only the min/max limits are really of any concern. As observed towards the end of the discussion (as of 2/11) Q1A prevents the load from back-powering the input of the circuit. It is commonly used in our chargers in this manner. The reason it is P-channel so that it does not need an extra “boost” supply to create a bias higher than the rest of the circuit, which will cost extra current to keep on. Q1B allows an alternative path for the battery to power the load rather than going through the top FET (Q2). When you remove input power Q2 will not switch, but it will still conduct battery current through the intrinsic body diode at a true silicon diode drop, causing power loss proportional to the load current, possibly blowing out the top FET due to excessive power dissipation. When the input is removed, R16 pull hard down on the Q1B gate to turn it on. D2 clamps the voltage from gate to source so that the limits are not exceeded on the FET when the input supply returns. It can be an N-channel too, but then you must derive the gate control as a positive bootstrapped voltage on top of the battery voltage to make Vg>Vs, so it is easily accomplished by a P-channel with no extra switching. If you connect the load to the charger output (“charger-fed”), a load cannot exceed battery charge limit. E.g. a 2A charge current limit could never supply more than 2A to a load demanding more current; the output would simply collapse to 0V if the load impedance was low enough. Somewhere in between would still starve the battery for current, causing the charge time to be extended. The arrangement in the demo circuit allows parallel operation of the load while fully charging the battery, assuming the input current limit has not been reached. Relays in battery charger circuits are a bad idea because they take so long to turn on/off, causing the output of the charger to see a high impedance very quickly. This can cause the energy that was trying to make its way to the battery to temporarily raise the output capacitor voltage beyond the programmed amount. This “boosting” can run through the top FET body diode actually getting sent back to the input.

shabaz · Answer

I'd go with the ones used in their eval board here . 20.5V is borderline higher than 20V so determining the effect of RDSon without any further details may need to be experimental. The MOSFETs in their eval board look appropriate for your charge voltage, assuming the input is less than 25V or so (to not operate against max thresholds). The gate voltage of both the MOSFETs is low, and the datasheet specifies the p-channel gate voltage range (VCLP-VTGATE) to be well below -20V for the on condition (and below 50mV when off, so the MOSFETs will certainly switch off) and you're safe there too. I havn't confirmed power dissipation you should expect, but that should be an easy calculation, based on the RDSon value, and is likely fine.