AMIC - A29010-70F - MEMORY, FLASH, NOR, 5V, 1M, 32DIP

AMIC - A29010-70FA29010-70F - MEMORY, FLASH, NOR, 5V, 1M, 32DIP | Buy Now!Buy Now!

128K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory

A29010 Series

128K X 8 Bit CMOS 5.0 Volt-only,

Uniform Sector Flash Memory

General Description

The A29010 is a 5.0 volt-only Flash memory organized as 131,072 bytes of 8 bits each. The 128 Kbytes of data are further divided into four sectors for flexible sector erase capability. The 8 bits of data appear on I/O0 - I/O7 while the addresses are input on A0 to A16. The A29010 is offered in 32-

pin PLCC, TSOP, and PDIP packages. This device is designed to be programmed in-system with the standard system 5.0 volt VCC supply. Additional 12.0 volt VPP is not required for insystem write or erase operations.

However, the A29010 can also be programmed in standard EPROM programmers. The A29010 has the first toggle bit, I/O6, which indicates whether an Embedded Program or Erase is in progress, or it is in the Erase Suspend. Besides the I/O6 toggle bit, the A29010 has a second toggle bit, I/O2, to indicate whether the addressed sector is being selected for erase. The A29010 also offers the ability to program in the Erase Suspend mode. The standard A29010 offers access times of 55, 70 and 90 ns allowing highspeed microprocessors to operate without wait states.

To eliminate bus contention the device has separate chip enable (CE), write enable (WE ) and output enable (OE ) controls. The device requires only a single 5.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The A29010 is entirely software command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.

Device programming occurs by writing the proper program command sequence. This initiates the Embedded Program algorithm - an internal algorithm that automatically times the program pulse widths and verifies proper program margin. Device erasure occurs by executing the proper erase

command sequence. This initiates the Embedded Erase algorithm - an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the

erase operation. During erase, the device automatically times the erase pulse widths and verifies proper erase margin.

The host system can detect whether a program or erase operation is complete by reading the I/O7 (Data Polling) and I/O6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The A29010 is fully erased when shipped from the factory. The hardware sector protection feature disables operations for both program and erase in any combination of the sectors of memory. This can be achieved via programming equipment.

The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any other sector that is not selected for erasure. True background erase can thus be achieved. Power consumption is greatly reduced when the device is placed in the standby mode.

Absolute Maximum Ratings

Ambient Operating Temperature . ……………..-55°C to + 125°C

Storage Temperature …………………………-65°C to + 125°C

Ground to VCC ……………………………………..-2.0V to 7.0V

Output Voltage (Note 1) ……………………………-2.0V to 7.0V

A9 &OE (Note 2) …………………………………..-2.0V to 12.5V

All other pins (Note 1)……………………………….. -2.0V to 7.0V

Output Short Circuit Current (Note 3) ………………………00mA

Notes:

1. Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, inputs may undershoot VSS to -2.0V for periods of up to 20ns. Maximum DC voltage on output and I/O pins is VCC +0.5V. During voltage transitions, outputs may overshoot to VCC +2.0V for periods up to 20ns.
2. Minimum DC input voltage on A9 pins is -0.5V. During voltage transitions, A9 andOE may overshoot VSS to -2.0V for periods of up to 20ns. Maximum DC input voltage on A9 and OE is +12.5V which may overshoot to 13.5V for periods up to 20ns.
3. No more than one output is shorted at a time. Duration of the short circuit should not be greater than one second.

*Comments

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of these specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.

Operating Ranges

Commercial (C) Devices

Ambient Temperature (TA) . . . . ……... . . . . . . . . . 0°C to +70°C

Operating Ranges:

Extended Range Device

Ambient Temperature(TA)………………………..…-40°C to 85°C

VCC Supply Voltages

VCC for ± 10% devices . . . . . . . . . . ………. . . . +4.5V to +5.5V

Operating ranges define those limits between which the functionally of the device is guaranteed.

Device Bus Operations

This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command.

The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The appropriate device bus operations table lists the inputs and control levels required, and the resulting output. The following subsections describe each of these operations in further detail.