Wow, apart from the TMP112 everything listed here is in QFN or BGA package. If its really a requirement for the challenge this will be fun for everybody. Or will there be evaluation boards available (the LMP910x0 ones look interesting)?
I think solder paste will be mandatory as one of the component purchases. Either that, or use evaluation boards. Will be interesting to see what methods people use to solder these. michaelkellett has mentioned using a hot plate to solder these. Another method I've heard is a hot air gun, but that sounds more difficult to get right without toasting the chip, but I could be wrong.
Flux would be another good thing to purchase (and tweezers, and a magnifier and very fine solder, and desoldering braid, and spare chips to experiment with) and then they may be hand-solderable with a fine tipped soldering iron (some youtube videos show a few procedures), if the pads are created with space to place the soldering iron tip right up against the edge of the ic and exposed copper on the pcb.
I've got my boards ( a bit later than I hoped) with the 0.5mm pitch BGAs. I've so far soldered 2 of the 64 pin parts down (STM32F100RBH6B). One I broke off to look at the quality of the joints - the other is working as far as I can test it without completing the board.
The tools required for this were: microscope, sticky flux, tweezers, thermocouple based thermometer, Kapton tape and the domestic hotplate I posted a picture of in the other thread.
If any one is interested in actually doing this I'll try to find time to post some pictures.
(BTW the biggest expense so far is the boards with 6 layers and 0.075mm track and gap rules - about £400 min order quantity. I have a feeling that it is possible to layout a board for the Lattice 132 pin 0.5mm BGA using OSH Park's 0.125mm process because Lattice leave some rows unpopulated which makes 'escape' tracks much easier.)
Here's a picture of the processor on the board, I won't have time to do some step by step video or pictures for a couple of weeks.
The chip is a bit hidden by the test connector. You can see the sparse pinning on the two Lattice 132 pin footprints. The pads are about 0.27mm diameter.
Here's a picture of the processor on the board, I won't have time to do some step by step video or pictures for a couple of weeks.
The chip is a bit hidden by the test connector. You can see the sparse pinning on the two Lattice 132 pin footprints. The pads are about 0.27mm diameter.
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