Hi Friends , In this Post we deal with Important Aspect in every design - "Debugging" 
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I would like to make this Post more generalized so that it can be applied to what ever Project you are working on it does not matter , for Reference i will use the PWM controlled LED design Project i posted here.
You may not require to go there as i tried my level best to make this Self Contained with much smaller number of references as possible.
Lets Dive Into Debugging .
As always in Our Top Down approach , Debugging is done in 2 scenarios :
1.)When you got both Software (PS programmed) and Hardware Logic (Bitstream of PL ) also Done
2.)When you are Building only PL logic or Some IP blocks in PL i.e.., In short You Don't have Your PS not Programmed Readily
We First Consider the First Case and Integrate the Second Case.
Debugging - When Both Software & Hardware Designs are Completed :
In this case , In order to debug , you have to add ILA (Integrated Logic Analyzer ) IP block into your PL Design and Attach the Line states or Pins/Ports you would like to Observe to the ILA probes Inputs just as shown in below figure.
Here we need to give PL fabric Clock from PS (for eg:FCLK_CLK0 ) ILA 'clk' Input and the Probes lengths are varied based on the Width of the Lines we connect to it.
Then you Generate the Bitstream and use that bitstream while Programing your FPGA in SDK .
When you are Running the Program on the Minized Open In Vivado the Hardware Manager Option , Under Program and Debug Heading (below Generate Bitstream).
If the Hardware Manager Prompts 'No Hardware Target is Open' select "Open Target " beside it and select "Auto Connect"
Vivado Connects to the Minized Device and gives the Possible Probe Interfaces you can See as Attached Probes, as shown in fig:
Here On the Hardware Tab you can See XADC , hw_ila_1(ILA) , hw_axi_1(jtag to axi interface).
XADC is already Integrated in the Logic Analyzer block , it is nothing by a scope or Xilinx Analog to Digital Convertor , a self explanatory name !
hw_ila_1 refers to the ILA which shows that it is in IDLE mode i.e.., It is not Capturing any Events on the Probes , you can Select the "hw_ila_1" interface (or similar to that name in your Design) and click "Run Trigger Immediate for this ILA Core" as show in Red Mark below :
This Gives the Immediate Logic Values on the Probes at that Moment .
Similarly you can go for Continuous Capture where you get Data on Probes Flowing Real Time continuously just as you were using some Logic Scope .
It also gives you a feature in which you tell Vivado to Capture the Traffic (Am i Irritating ?) .
For that Feature , you first select which Logic Probes are best suited for that (Interrupt pins are used in such cases) , Go for Trigger Setup
Select the '+' button and Set the Value to when you want Capture to Start (R for +ve Edge Triggering and soon)
That's it , you can observe that ILA is in waiting State as long as there are no triggers
Here the Default setting is that the ILA prints Half of the Samples(512 in my Case) before Triggering and rest after Triggering , we can change it if required.
In this way , we can use Vivado Integrated Logic Analyzer to Debug our Design , It can also be used to work as a Logic Analyzer Yeah , we can Build a one .
I will build a USB Logic Analyzer and will demonstrate it in my Future Post.
In the mean time , i would post about Software Design Training I am Undergoing , it fills the Holes in our Understanding .
Don't Forget , I will continue Posting the Hardware Aspects also along with Software Training (but Separate Posts) , as there is lot of Fun waiting for Us .
See You in my Next Post.