In the previous blog post Path to Programmable Blog 5 - Creating Custom IP , we created custom IP which comprised of some HDL code that implemented a PWM controller, which was then connected to the AXI bus as an AXI-4 Lite Slave, allowing the PS to control the PWM controller. We also added an Integrated Logic Analyzer and JTAG-AXI core.
HW Chapter 9 video: Vivado's Hardware Manager
This video went over the different debugging techniques:
Although the ILA is implemented in the FPGA fabric along with the main design, it is fully programmable at run time & can be customized with probe comparators, counters & flags.
The JTAG-AXI core allows the user to interact with the AXI bus without the CPU present, since it is also a master to the interconnect. Users can issue commands to execute AXI bus interactions, allowing hardware engineers to test & debug AXI peripherals without actually having any software running on the CPU.
Lab 8 - Hardware Debugging Zynq Designs
We start by exporting the implemented design that we created in the preceding blog post.
In Xilinx SDK, generate a new BSP, and import the previous projects (BRAM_DMA, Hello World, Memory & Peripheral Tester).
Create a new 'Empty Application', and then import the provided "LED_Dimmer_Int.c" file into sources. This file contains code that reads a value from the UART, converts it to a PWM value and writes it to the register in the PWM Controller. It also sets up an Interrupt Service Routine to handle Interrupts from the PWM Controller.
To test all this out, we program the bitstream, open up a serial terminal and run the example.
Entering any value from 0-9 sets a different value, and the brightness of the LED on the MiniZed varies accordingly. Entering any other character causes an Interrupt (due to the value in the PWM Controller register), which resets the brightness to 0.
To get started with hardware debugging, go back to Vivado and open the Hardware Manager. Connect to the board, and the detected debug cores will show up. Clicking on 'capture' will display the status of the signals connected to the ILA (assuming the ILA core was selected), just like a logic analyzer.
Like any logic analyzer, you can set it to automatically trigger based on the value of a signal (eg rising edge of the interrupt line in this case).
Another way of debugging/testing is to use the AXI-JTAG core, which lets you take control of the bus so that you can issue commands that trigger transactions as shown:
This part of the lab involved executing a couple o TCL commands to perform reads & writes to addresses on the AXI bus i.e. PWM Controller registers and the BRAM.
HW Chapter 10 video: TCL Scripting
This video highlighted the advantages of TCL scripting. TCL allows users to automate builds & backups, so importing a new project only involves running the script, which will add the necessary files, IP and even make connections. Without TCL, users would have had to spend hours configuring everything via the GUI when rebuilding on importing projects.
Lab 9 - The Power of Scripting using Tcl
We started off this lab by running a TCL script that was provided in the supporting documents.
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The script did quite a lot: it added I2C, UART & GPIO AXI slaves, a wireless manager, extra ports, connected all of them, merged the interrupt sources and imported additional constraints.
The lab document goes through the TCL script and tries to briefly explain what some of the commands did.
HW Chapter 11 video: What's Next
This video summarized some learning resources, portfolio etc.of Xilinx and Avnet:
- Xilinx HLS: Next Generation High Level Design Tools which Abstract the hardware from the user.
- Free and Commercial Software Development Tools.
- Portfolio of development boards, reference designs, ready to use IP, documentation etc.
- For support visit zedboard.org or the Xilinx forums
HW Chapter 9 video: Vivado's Hardware Manager
Lab 8 - Hardware Debugging Zynq Designs
HW Chapter 10 video: TCL Scripting
Lab 9 - The Power of Scripting using Tcl
With this, the Module 1 of Path to Programmable "Developing Zynq Hardware" is complete!
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