In this lab we will create a Block RAM in the programmable logic which can be used to buffer data going between the PS and PL.
1. How to add BRAM from IP Catalog
Open block design with ZYNQ7 processing system. Choose the Add IP button on the shortcut bar of the diagram. From the IP Catalog select option AXI BRAM Controller.
Double click the AXI BRAM Controller and customize IP. We need to increase Data Width to 64 bits and change Support for AXI Narrow Bursts to Manual. Then click OK and choose option Run Connection Automation.
In the popup choose All Automation and click OK. This assistant has automatically added and connected a Block Memory Generator to IP block.
2. How to connect AXI interconnect and build
In this step we will enable master AXI interconnect on the PS, master clock from the PS. Then we will connect all IP to the PS.
Double click on the ZYNQ7 PS and select 32b GP AXI Master Ports. Please enable M AXI GP0 interface. We need to check if FCLK_CLK0. is set to 50MHz at Clock Configuration page.FCLK_CLK0.
Then please close OK and Run Connection Automation. Make sure that you choose a "New AXI Interconnect" Interconnect IP type. Now we need to check the address space for BRAM on the AXI interface. To do that please go to Window and choose option Address Editor.
Now we need to validate design. Please choose option Validate Design. After that we could save block design and generate bitstream.
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