[PP-08] Lab 5 - Adding a peripheral in programmable logic

10 Nov 2018

In this lab we will create a Block RAM in the programmable logic which can be used to buffer data going between the PS and PL.

1. How to add BRAM from IP Catalog

Open block design with ZYNQ7 processing system. Choose the Add IP button on the shortcut bar of the diagram. From the IP Catalog select option AXI BRAM Controller.

Double click the AXI BRAM Controller and customize IP. We need to increase Data Width to 64 bits and change Support for AXI Narrow Bursts to Manual. Then click OK and choose option Run Connection Automation.

In the popup choose All Automation and click OK. This assistant has automatically added and connected a Block Memory Generator to IP block.

2. How to connect AXI interconnect and build

In this step we will enable master AXI interconnect on the PS, master clock from the PS. Then we will connect all IP to the PS.

Double click on the ZYNQ7 PS and select 32b GP AXI Master Ports. Please enable M AXI GP0 interface. We need to check if FCLK_CLK0. is set to 50MHz at Clock Configuration page.FCLK_CLK0.

Then please close OK and Run Connection Automation. Make sure that you choose a "New AXI Interconnect" Interconnect IP type. Now we need to check the address space for BRAM on the AXI interface. To do that please go to Window and choose option Address Editor.

Now we need to validate design. Please choose option Validate Design. After that we could save block design and generate bitstream.

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michaelkellett over 6 years ago

This is all very well, but could you please explain the point of it all.

You've connected both ports of a block RAM to the Zynq processor - via an AXI block RAM controller - according to the introduction this will buffer data going between the PS to the PL.

For those of us not steeped in Xlinx jargon,

What are the PS and the PL and how does the block diagram, is this a complete thing, and what does it actually do ?

I can't see any way that data gets out from the BRAM to Programmable Logic (my guess at what PL is).

MK
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kk99 over 6 years ago in reply to michaelkellett

As you written, in this lab we have created BRAM module in PL (Programmable Logic) for which have access a PS (Processing System) via AXI interconnect. You learned here how to:
- add a BRAM from IP Catalog,
- connect AXI peripherals to the Zynq PS.
After that you could use this configuration in SDK which is done in next laboratory 6 (lab6), where we have example application which transfers data.
Additionally you could create your own, additional module in PL which uses data from BRAM.
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michaelkellett over 6 years ago in reply to kk99

Thanks for explaining - I'll look at Lab6.

MK
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michaelkellett over 6 years ago in reply to michaelkellett

Have now looked at 6.

The BRAM seems to be an isolated island in the logic with no connection to external logic and no ports available to connect to external logic.

The BRAM seems to be accessible to the ARM core.

The lab 6 screen dumps seem to show that you run some unknown code to test this connection and that it goes quicker if you use DMA.

Do we ever get to the bit where the BRAM is actually connected to external logic - it seems to have no free ports to make this possible.

MK
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kk99 over 6 years ago in reply to michaelkellett

Yes, it is simple example how to use created in PL BRAM to transfer data from/to PS with usage of DMA in PS. The source of test application you could find here:
https://github.com/Xilinx/linux-xlnx/blob/master/drivers/dma/dmatest.c

If you created a additional logic which would like to have access for e.g. BRAM, you need just to connect this device as slave to Slave Interconnect. I suppose that it will be a purpose of laboratory number 7.
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michaelkellett over 6 years ago in reply to kk99

Thanks for your patience (and responses).

Looking forward to Lab 7 !

MK
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kk99 over 6 years ago in reply to michaelkellett

You are welcome. Now I am going through the course syllabus and after that I will start my own modifications.
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kk99 over 6 years ago in reply to michaelkellett

You are welcome. Now I am going through the course syllabus and after that I will start my own modifications.
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