During roadtest of Arty S7 I have created a simple PMOD module with single segment display. So, I decided to use it with MiniZed SoC to create example application. I have a driver for single segment display written in Verilog. I used a top module to generate test pattern for this display module. ZYNQ7 processing system is required in this case in design to generate system clock used by top and display modules. Seven segment display is connected to PMOD1 connector. There are pinouts:
- L15 -> D,
- M15 -> C,
- L14 -> B,
- M14 -> A,
- K13 -> DP,
- L14 -> G,
- N13 -> F,
- N14 -> E.
First we need to create a empty project for MiniZed board. You could use a MiniZed board definitions available at Avnet page. Then please choose "Create Block Design" and add a ZYNQ7 PS. Please edit ZYNQ7 PS properties:
- change FCLK_CLK0 to 100 MHz,
- disable M AXI GPO interface.
Then please run "Run Block Automation" and "Create HDL Wrapper" for design.
Now you need to import top.v and display.v sources and top.xdc constraints. They are available in attachment. Please put top design at diagram and connect "FCLK_CLK0" to "clock". Then please generate output products and bitstream.
After that please export hardware with included bitstream and launch sdk. In SDK you need to create a empty application. Then please run application and program FPGA. You should be able to see digits on display. Here is video from test run:
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