Introduction

As I had already mentioned in my application I have worked with FPGAs in the past for 2 years roughly including my masters thesis with the old Xilinx ISE. So I kind of have a basic sense of how FPGAs work and the background behind them. At the time I had also worked with Microblaze which was quite a sensation when the idea of soft-processor was amazing. It has become quite main-stream in the FPGAs today though. So one can say I am a legacy FPGA programmer.

After reading the new training material it is amazing to see how far and advanced the FPGAs have become with multiple soft-core processors capable of doing what not ***. There are also certain Xilinx ZYNQ devices with Dual Cortex-A9 MPCore and also to mention the Ultrascale+ series with Quad Cortex-A53 MPCore able to run @1.5GHz

The Xilinx Webpack can be freely downloaded from the website and one can easily start to play with sample code. In this training I am using the Vivado Design Suite 2017.4

Lab0

This lab focused on the installation of Xilinx Vivado WebPACK 2017.4; using Tera Term for serial communication and USB-UART drivers for the development board. I am working with windows edition. A trick during Vivado installation to reduce the memory usage by Vivado files is to un-check the devices that we donot need in this training such as Ultrascale and Virtex. By default Vivado tries to install everything which is really not needed and save the precious memory on the C: drive.

I tested it with the Xilinx Vivado WebPACK 2017.1 and Xilinx Vivado WebPACK 2017.4 installer.

Saved me some precious Disk Space !!!!!!!

Lab1

This lab was pretty simple first one. Here I made the first Vivado project targeted to MiniZed board loaded with the FPGA device xc7z007sclg225-1.

Next important step was to learn to customize the Zynq processing core

Customizing the ZYNQ and its peripherals can be done here

Lab2

Task1 : Enable and map a Zynq PS UART peripheral

The UART is set to UART1 peripheral with Baud Rate is set to 115200 in the Zynq PS.

And the clock setttings must be check for each board separately.

Task 2: Configure Memory and Clocks for the Zynq PS

For minized board Clock settings are:

• Input frequency is 33.333333 MHz
• CPU frequency is 666.666666 MHz
• DDR frequency is 533.333333 MHz

And also the correct DDR Memory Device must be set in DDR Configuration page. For Minized the DDR3 memory used is MT41K256M16RE-125

Also the correct DQS to Clock Delay and Board Delay settings has to be set. It is specified as delays in the PCB. The parameters are specific to each PCB design and Zynq package. The values are based on the PCB trace lengths and the specific Zynq package.

Task 3: Build the hardware platform

How the design is mapped on the device

The Schematic Overview

Quick Power Analysis of the design

Task 4: Export a design to SDK

After exporting the bitstream file from Vivado to the SDK

Task 5: Create and run a Hello World application

And... The Hello World runs successfully

Conclusion: As one may have noticed there are many steps involved from creating the simple hardware in Vivado to the correct settings for Zynq PS and finally migrating the board support files to run the Hello world in Vivado SDK software.