HI guys 
! This post is mainly Intended to Answer few Important Questions regarding why we are doing few things for Getting your Project Runing on Minized at First.
Here are the List of Questions this Post aims to Clarify,If you got few other Questions as well, Feel free to ask,I will make sure to give vivid picture regarding it.
NOTE : These Questions are actually created by guessing possible doubts users would encounter regarding my Previous post of "Hello World with Minized".
Questions 
:
While Dealing with Vivado:
1.Why Do we need to place the Zynq7 PS system IP in Vivado IP Intergrator ?
2.What Do block Automation do ?
3.Why we select some peripherals in MIO configuration to use through MIO and other as EMIO
4.Can you select different clock frequencies for the CPU,DDR clock , is there any criteria to be met ?
5.Why Do we create HDL wrapper after validating our Design
6.What is a Bit Stream file
7.Why should you export the Hardware for SDK
While Dealing with SDK:
8.Do I need to Use SDK
9.How does SDK will work based on my Hardware Design in Vivado
10.What is the Board Support Package , How it is Dependent on my Hardware Design
11.Why do you Need to Specify BSP for creating a new Application , How the Application is Executed with BSP
Lets Address Them !
1.Why Do we need to place the Zynq7 PS system IP in Vivado IP Intergrator ?
Minized is a Processesor First device , which means the PS (Processing System-Our ARM) starts at first and will configure the PL(Programable Logic - Our FPGA) such as the clocks required for PL are generated by PS PLL(Phase Locked Loop) for instance.
Moreover,the PS system is Hard IP(Intellectual Propery) meaning that the PS blocks are already there on the Silicon but the Peripherals and the Configurations(how PS should run) is selected by user by including the PS IP which generates the BitStream which is responsible to reflect that Configuration in PS.
for eg: Consider above Diagram,we usually set the CPU frequency,DDR frequency and I/O frequency in the Configuration window , vivado will generate Bitstream such that the Multiplexers are activated appropriately and the Divider may also be altered. By Disabling Clock to PL the Mux reroutes such that No clock reaches PL
2.What Do block Automation do ?
When we Add a new IP design(for Eg : consider zynq ps7 ) in IP-Integrator , and consider our design uses Ex-OR gate in PL fabric with the User Button as one Input and a signal from PS block ,Butt it is required to use an AXI Interconnect block to Connect a GPIO or Signal from PS to PL block , and Vivado is very smart enough to think about it so that when we Run Block Automation,we adds AXI interconnect IP and connects it between PS gpio and PL ex-or gate Input.
In this way Block Automation saves the Designer from Possible Pitfalls and reduces the Design time also .
Caution : Don't let tools take away the fun of Learning the Hard way from You ! 
3.Why we select some peripherals in MIO configuration to use through MIO and other as EMIO
MIO (Multiplexed I/O )pins are the pins that are connected to PS gpio pins where as EMIO is Extended-MIO which refers to PL pins.All peripherals cannot be connected to MIO as there are just 54 pins available (as shown below) , so based on the preference and some timing Constrains (for Eg:QSPI,USB) the Multiplexer maps 54 pins to the peripherals based on the data in Bitstream file which is generated by vivado from pin assignment in MIO configuration given by the User.
Usually when Assigning the MIO pins to peripherals in Configuration page , it is preferred to assign from top peripherals to bottom.
But the First Assignment should be made to QSPI (or SRAM or Flash meory) as it is responsible for Booting PS(remember PS starts at first before PL so that we cannot use QSPI/flash using EMIO ) and USB at Next is prefered as the EMIO doesnot meet the Timing Constrain imposed by USB protocol.
Base on this Criteria when we completed using MIO pins we can use the Peripherals through EMIO(their Access time is bit Slower)
Note:Gigabit Etherbet is routed through EMIO only.
4.Can you select different clock frequencies for the CPU, DDR clock , is there any criteria to be met ?
All the Clocks are generated from a Basic Clock signal Input Frequency (usually 33.33 MHz) and this signal is used to generate the DDR,CPU & IO clocks by using DDR PLL,ARM PLL ,IO PLL respectively for each of the Clocks.Usually DDR PLL,ARM PLL are follwed by a Divider by 2 block hence we need to set the DDR,ARM PLL to run at 2*Desired Frequency.
Note that PLLs generate Clock signals that are Integral Multiple of Input Frequency based on this Criteria we can set different operating Frequencies as Desired.
5.Why Do we create HDL wrapper after validating our Design ?
When we validate design successfully , it means our design (flow) has no errors and is in functional state but since we add IP design , it is instantiated as a component or some black box in our Whole Project (or Device , since it contains components in it).
Even you got 1 component in your Design you need it add an Enclosure to it(Just like we add an Enclosure for Minized Board) , this Enclosure is called as Wrapper.
So a Wrappper doesnot contain much of Logic, it just Declares our IPs used as Some Components and Instantiates that Components in the Architecture.
6.What is a Bit Stream file
In Programable Logic World (FPGAs) , hardware is programable in the Sense that the wires that are routed between different blocks is Configured (Based on the Technology ) and predefined logic blocks are configured to implement the Design (usually specified in HDL).
Bit Steam is the maping to the device such that the Routing of Wires and Logic Block configuration is acheived.
It is generated by EDA tools(eg. Vivado) by synthesizing the design and checking for any timing constrains given(eg: used in cases where Some signals are to be reached within specified time delay like 0.5ns etc. )
The PL block is structured (programed) into that Hardware Design by loading that Bit Stream into SRAM which connects to the Programable Interconnects there by implements that Design on Hardware.
7.Why should you export the Hardware for SDK
In Minized PSoC (Programmable System on Chip) the hardware Designers may be designing New blocks or Including IPs or Configuring the Existing Blocks , all these alters the Final Bit stream and the Implemented Design.
Simply we can say that In Order to tell the SDK that a Device has Those functionalities with Address maping for Interacting with PS or Use some Blocks (Such as UART enabled in Zynq PS 7 ip in vivado) , we need to export the Hardware Including Bitstream (Preferably) to SDK.
It's SDK part Folks !
8.Do I need to Use SDK ?
As stated Earlier Zynq (Minized) is PS first device , in order to implement your Design you have to
1. load all the Executable, PL bit stream and Boot loader on to flash
(or)
2.Run it using USB jtag to load it into DDR to Execute the design.
Since we are dealing with ARM core PS , we employ Software Development IDE tool like Xilinx SDK (based on Eclipse ) for generating the .elf (executable) with Board support Package and First Stage Boot Loader (if any) to the Design.
9.How does SDK will work based on my Hardware Design in Vivado
When we export our Hardware Design from Vivado to SDK , SDK gets .hdf , .init files which are the Addresses to be used to map to various blocks,peripherals etc. all given by Vivado so that any custom harware design can also be Implemented easily , It gives all the Low Level Details (memory Address Maps , Initialization Values such as for Clocks etc. and many more ) , By using all these SDK gets an Idea of what it can use , where it should call to for a perticular function or Interrupt and soon
10.What is the Board Support Package , How it is Dependent on my Hardware Design
If we see the init files(hardware defination files) in SDK as low level implementations details , we get help from Board Support Package (BSP) which are generated by SDK which gives a level of Abstraction to these Low Level hardware design details by creating Drivers for the Peripherals and blocks we included in the Design (For Eg:Generates Drivers for Interfacing to UART if it is Enabled in Vivado Configuration page)
BSP is Dependent on the Exported Hardware Design as it is used by SDK to generate BSP to support only the peripherals Included/Enabled in the Hardware Design with their given Address Map by Vivado by giving Drivers for those Peripherals using their Addresses.
11.Why do you Need to Specify BSP for creating a new Application , How the Application is Executed with BSP
When we Create a New Application, we need to specify the BSP as it is the One which Contains Drivers and the Required Libraries (i.e., It includes Functions for Operating on Peripherals through PS) so that a simple function call using that BSP can Accomplish our Task and there by relieves us from the Hectic of Worrying about low level details.
So We can Think the Application Program as a Top Layer of Abstraction Contacting the BSP, the BSP in turn contacts with the Low Level Functionality files for Accomplishing the Task given in Application Program.
I hope you guys feel better to Work with these Tools by Knowing few Details regarding How they are Implemented, as always please feel free to ask if you have any Questions or unable to understand them Properly.
See You Guys in my Next Post
